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From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Thu, 12 Jul 2018 13:41:39 +0200
Subject: Some spelling errors fixed
---
manual/CHAPTER_Overview.tex | 2 +-
manual/command-reference-manual.tex | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index 2feb0f1..c7d1d5c 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -240,7 +240,7 @@ An RTLIL::Wire object has the following properties:
As with modules, the attributes can be Verilog attributes imported by the
Verilog frontend or attributes assigned by passes.
-In Yosys, busses (signal vectors) are represented using a single wire object
+In Yosys, buses (signal vectors) are represented using a single wire object
with a width > 1. So Yosys does not convert signal vectors to individual signals.
This makes some aspects of RTLIL more complex but enables Yosys to be used for
coarse grain synthesis where the cells of the target architecture operate on
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index bed6326..eb43467 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -3182,7 +3182,7 @@ to a graphics file (usually SVG or PostScript).
assigned to each unique value of this attribute.
-width
- annotate busses with a label indicating the width of the bus.
+ annotate buses with a label indicating the width of the bus.
-signed
mark ports (A, B) that are declared as signed (using the [AB]_SIGNED
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