summaryrefslogtreecommitdiff
path: root/manual/FILES_Eval/or1200.prj
blob: 9496874e0828ae79292094e39856cb7be0b12ed2 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_spram.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_reg2mem.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_mem2reg.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dpram.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_amultp2_32x32.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_wbmux.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_sprs.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_rf.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_operandmuxes.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_mult_mac.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_lsu.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_immu_tlb.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_if.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_tag.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_ram.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_fsm.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_genpc.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_freeze.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_fpu.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_except.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dmmu_tlb.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ctrl.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_cfgr.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_alu.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_wb_biu.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_tt.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_sb.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_qmem_top.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_pm.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_pic.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_immu_top.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_top.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_du.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dmmu_top.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dc_top.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_cpu.v"
verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_top.v"