manual/FILES_StateOfTheArt/always01_pub.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14

module uut_always01(clock,
		reset, count);

input clock, reset;
output [3:0] count;
reg [3:0] count;

always @(posedge clock)
	count <= reset ?
		0 : count + 1;


endmodule