path: root/manual/PRESENTATION_ExAdv.tex

\section{Yosys by example -- Advanced Synthesis}

\begin{frame}
\sectionpage
\end{frame}

\begin{frame}{Overview}
This section contains 4 subsections:
\begin{itemize}
\item Using selections
\item Advanced uses of techmap
\item Coarse-grain synthesis
\item Automatic design changes
\end{itemize}
\end{frame}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\subsection{Using selections}

\begin{frame}
\subsectionpage
\subsectionpagesuffix
\end{frame}

\subsubsection{Simple selections}

\begin{frame}[fragile]{\subsubsecname}
Most Yosys commands make use of the ``selection framework'' of Yosys. It can be used
to apply commands only to part of the design. For example:

\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
delete                # will delete the whole design, but

delete foobar         # will only delete the module foobar.
\end{lstlisting}

\bigskip
The {\tt select} command can be used to create a selection for subsequent
commands. For example:

\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select foobar         # select the module foobar
delete                # delete selected objects
select -clear         # reset selection (select whole design)
\end{lstlisting}
\end{frame}

\subsubsection{Selection by object name}

\begin{frame}[fragile]{\subsubsecname}
The easiest way to select objects is by object name. This is usually only done
in synthesis scripts that are hand-tailored for a specific design.

\bigskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select foobar         # select module foobar
select foo*           # select all modules whose names start with foo
select foo*/bar*      # select all objects matching bar* from modules matching foo*
select */clk          # select objects named clk from all modules
\end{lstlisting}
\end{frame}

\subsubsection{Module and design context}

\begin{frame}[fragile]{\subsubsecname}
Commands can be executed in {\it module\/} or {\it design\/} context. Until now all
commands have been executed in design context. The {\tt cd} command can be used
to switch to module context.

\bigskip
In module context all commands only effect the active module. Objects in the module
are selected without the {\tt <module\_name>/} prefix. For example:

\bigskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
cd foo                # switch to module foo
delete bar            # delete object foo/bar

cd mycpu              # switch to module mycpu
dump reg_*            # print details on all objects whose names start with reg_

cd ..                 # switch back to design
\end{lstlisting}

\bigskip
Note: Most synthesis scripts never switch to module context. But it is a very powerful
tool for interactive design investigation.
\end{frame}

\subsubsection{Selecting by object property or type}

\begin{frame}[fragile]{\subsubsecname}
Special pattern can be used to select by object property or type. For example:

\bigskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select w:reg_*        # select all wires whose names start with reg_
select a:foobar       # select all objects with the attribute foobar set
select a:foobar=42    # select all objects with the attribute foobar set to 42
select A:blabla       # select all modules with the attribute blabla set
select foo/t:$add     # select all $add cells from the module foo
\end{lstlisting}

\bigskip
A complete list of this pattern expressions can be found in the command
reference to the {\tt select} command.
\end{frame}

\subsubsection{Combining selection}

\begin{frame}[fragile]{\subsubsecname}
When more than one selection expression is used in one statement they are
pushed on a stack. The final elements on the stack are combined into a union:

\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select t:$dff r:WIDTH>1     # all cells of type $dff and/or with a parameter WIDTH > 1
\end{lstlisting}

\bigskip
Special \%-commands can be used to combine the elements on the stack:

\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select t:$dff r:WIDTH>1 %i  # all cells of type $dff *AND* with a parameter WIDTH > 1
\end{lstlisting}

\medskip
\begin{block}{Examples for {\tt \%}-codes (see {\tt help select} for full list)}
{\tt \%u} \dotfill union of top two elements on stack -- pop 2, push 1 \\
{\tt \%d} \dotfill difference of top two elements on stack -- pop 2, push 1 \\
{\tt \%i} \dotfill intersection of top two elements on stack -- pop 2, push 1 \\
{\tt \%n} \dotfill inverse of top element on stack -- pop 1, push 1 \\
\end{block}
\end{frame}

\subsubsection{Expanding selections}

\begin{frame}[fragile]{\subsubsecname}
Selections of cells and wires can be expanded along connections using {\tt \%}-codes
for selecting input cones ({\tt \%ci}), output cones ({\tt \%co}), or both ({\tt \%x}).

\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
# select all wires that are inputs to $add cells
select t:$add %ci w:* %i
\end{lstlisting}

\bigskip
Additional constraints such as port names can be specified.

\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
# select all wires that connect a "Q" output with a "D" input
select c:* %co:+[Q] w:* %i c:* %ci:+[D] w:* %i %i

# select the multiplexer tree that drives the signal 'state'
select state %ci*:+$mux,$pmux[A,B,Y]
\end{lstlisting}

\bigskip
See {\tt help select} for full documentation of this expressions.
\end{frame}

\subsubsection{Incremental selection}

\begin{frame}[fragile]{\subsubsecname}
Sometime a selection can most easily described by a series of add/delete operations.
The commands {\tt select -add} and {\tt select -del} respectively add or remove objects
from the current selection instead of overwriting it.

\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select -none            # start with an empty selection
select -add reg_*       # select a bunch of objects
select -del reg_42      # but not this one
select -add state %ci   # and add mor stuff
\end{lstlisting}

\bigskip
Within a select expression the token {\tt \%} can be used to push the previous selection
on the stack.

\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select t:$add t:$sub    # select all $add and $sub cells
select % %ci % %d       # select only the input wires to those cells
\end{lstlisting}
\end{frame}

\subsubsection{Creating selection variables}

\begin{frame}[fragile]{\subsubsecname}
Selections can be stored under a name with the {\tt select -set <name>}
command. The stored selections can be used in later select expressions
using the syntax {\tt @<name>}.

\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select -set cone_a state_a %ci*:-$dff  # set @cone_a to the input cone of state_a
select -set cone_b state_b %ci*:-$dff  # set @cone_b to the input cone of state_b
select @cone_a @cone_b %i              # select the objects that are in both cones
\end{lstlisting}

\bigskip
Remember that select expressions can also be used directly as arguments to most
commands. Some commands also except a single select argument to some options.
In those cases selection variables must be used to capture more complex selections.

\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
dump @cone_a @cone_b

select -set cone_ab @cone_a @cone_b %i
show -color red @cone_ab -color magenta @cone_a -color blue @cone_b
\end{lstlisting}
\end{frame}

\begin{frame}[fragile]{\subsubsecname{} -- Example}
\begin{columns}
\column[t]{4cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/select.v}
\column[t]{7cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExAdv/select.ys}
\end{columns}
\hfil\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/select.pdf}
\end{frame}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\subsection{Advanced uses of techmap}

\begin{frame}
\subsectionpage
\subsectionpagesuffix
\end{frame}

\subsubsection{Introduction to techmap}

\begin{frame}{\subsubsecname}
\begin{itemize}
\item
The {\tt techmap} command replaces cells in the design with implementations given
as verilog code (called ``map files''). It can replace Yosys' internal cell
types (such as {\tt \$or}) as well as user-defined cell types.
\medskip\item
Verilog parameters are used extensively to customize the internal cell types.
\medskip\item
Additional special parameters are used by techmap to communicate meta-data to the
map files.
\medskip\item
Special wires are used to instruct techmap how to handle a module in the map file.
\medskip\item
Generate blocks and recursion are powerful tools for writing map files.
\end{itemize}
\end{frame}

\begin{frame}[t]{\subsubsecname{} -- Example 1/2}
\vskip-0.2cm
To map the Verilog OR-reduction operator to 3-input OR gates:
\vskip-0.2cm
\begin{columns}
\column[t]{0.35\linewidth}
\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=24]{PRESENTATION_ExAdv/red_or3x1_map.v}
\column[t]{0.65\linewidth}
\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=25]{PRESENTATION_ExAdv/red_or3x1_map.v}
\end{columns}
\end{frame}

\begin{frame}[t]{\subsubsecname{} -- Example 2/2}
\vbox to 0cm{
\hfil\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/red_or3x1.pdf}
\vss
}
\begin{columns}
\column[t]{6cm}
\column[t]{4cm}
\vskip-0.6cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, firstline=4, lastline=4, frame=single]{PRESENTATION_ExAdv/red_or3x1_test.ys}
\vskip-0.2cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/red_or3x1_test.v}
\end{columns}
\end{frame}

\subsubsection{Conditional techmap}

\begin{frame}{\subsubsecname}
\begin{itemize}
\item In some cases only cells with certain properties should be substituted.
\medskip
\item The special wire {\tt \_TECHMAP\_FAIL\_} can be used to disable a module
in the map file for a certain set of parameters.
\medskip
\item The wire {\tt \_TECHMAP\_FAIL\_} must be set to a constant value. If it
is non-zero then the module is disabled for this set of parameters.
\medskip
\item Example use-cases:
\begin{itemize}
\item coarse-grain cell types that only operate on certain bit widths
\item memory resources for different memory geometries (width, depth, ports, etc.)
\end{itemize}
\end{itemize}
\end{frame}

\begin{frame}[t]{\subsubsecname{} -- Example}
\vbox to 0cm{
\vskip-0.5cm
\hfill\includegraphics[width=6cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/sym_mul.pdf}
\vss
}
\vskip-0.5cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/sym_mul_map.v}
\begin{columns}
\column[t]{6cm}
\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/sym_mul_test.v}
\column[t]{4cm}
\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=4]{PRESENTATION_ExAdv/sym_mul_test.ys}
\end{columns}
\end{frame}

\subsubsection{Scripting in map modules}

\begin{frame}{\subsubsecname}
\begin{itemize}
\item The special wires {\tt \_TECHMAP\_DO\_*} can be used to run Yosys scripts
in the context of the replacement module.
\medskip
\item The wire that comes first in alphabetical oder is interpreted as string (must
be connected to constants) that is executed as script. Then the wire is removed. Repeat.
\medskip
\item You can even call techmap recursively!
\medskip
\item Example use-cases:
\begin{itemize}
\item Using always blocks in map module: call {\tt proc}
\item Perform expensive optimizations (such as {\tt freduce}) on cells where
this is known to work well.
\item Interacting with custom commands.
\end{itemize}
\end{itemize}

\scriptsize
PROTIP: Commands such as {\tt shell}, {\tt show -pause}, and {\tt dump} can be use
in the {\tt \_TECHMAP\_DO\_*} scripts for debugging map modules.
\end{frame}

\begin{frame}[t]{\subsubsecname{} -- Example}
\vbox to 0cm{
\vskip4.2cm
\hskip0.5cm\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mymul.pdf}
\vss
}
\vskip-0.6cm
\begin{columns}
\column[t]{6cm}
\vskip-0.6cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mymul_map.v}
\column[t]{4.2cm}
\vskip-0.6cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mymul_test.v}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mymul_test.ys}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, frame=single, language=ys, firstline=7, lastline=12]{PRESENTATION_ExAdv/mymul_test.ys}
\end{columns}
\end{frame}

\subsubsection{Handling constant inputs}

\begin{frame}{\subsubsecname}
\begin{itemize}
\item The special parameters {\tt \_TECHMAP\_CONSTMSK\_\it <port-name>\tt \_} and
{\tt \_TECHMAP\_CONSTVAL\_\it <port-name>\tt \_} can be used to handle constant
input values to cells.
\medskip
\item The former contains 1-bits for all constant input bits on the port.
\medskip
\item The latter contains the constant bits or undef (x) for non-constant bits.
\medskip
\item Example use-cases:
\begin{itemize}
\item Converting arithmetic (for example multiply to shift)
\item Identify constant addresses or enable bits in memory interfaces.
\end{itemize}
\end{itemize}
\end{frame}

\begin{frame}[t]{\subsubsecname{} -- Example}
\vbox to 0cm{
\vskip5.2cm
\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mulshift.pdf}
\vss
}
\vskip-0.6cm
\begin{columns}
\column[t]{6cm}
\vskip-0.4cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mulshift_map.v}
\column[t]{4.2cm}
\vskip-0.6cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mulshift_test.v}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mulshift_test.ys}
\end{columns}
\end{frame}

\subsubsection{Handling shorted inputs}

\begin{frame}{\subsubsecname}
\begin{itemize}
\item The special parameters {\tt \_TECHMAP\_BITS\_CONNMAP\_} and
{\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} can be used to handle shorted inputs.
\medskip
\item Each bit of the port correlates to an {\tt \_TECHMAP\_BITS\_CONNMAP\_} bits wide
number in {\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_}.
\medskip
\item Each unique signal bit is assigned its own number. Identical fields in the {\tt
\_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} parameters mean shorted signal bits.
\medskip
\item The numbers 0-3 are reserved for {\tt 0}, {\tt 1}, {\tt x}, and {\tt z} respectively.
\medskip
\item Example use-cases:
\begin{itemize}
\item Detecting shared clock or control signals in memory interfaces.
\item In some cases this can be used for for optimization.
\end{itemize}
\end{itemize}
\end{frame}

\begin{frame}[t]{\subsubsecname{} -- Example}
\vbox to 0cm{
\vskip4.5cm
\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/addshift.pdf}
\vss
}
\vskip-0.6cm
\begin{columns}
\column[t]{6cm}
\vskip-0.4cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/addshift_map.v}
\column[t]{4.2cm}
\vskip-0.6cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/addshift_test.v}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/addshift_test.ys}
\end{columns}
\end{frame}

\subsubsection{Notes on using techmap}

\begin{frame}{\subsubsecname}
\begin{itemize}
\item Don't use positional cell parameters in map modules.
\medskip
\item Don't try to implement basic logic optimization with techmap. \\
{\small (So the OR-reduce using OR3X1 cells map was actually a bad example.)}
\medskip
\item You can use the {\tt \$\_\,\_}-prefix for internal cell types to avoid
collisions with the user-namespace. But always use two underscores or the
internal consistency checker will trigger on this cells.
\medskip
\item Techmap has two major use cases:
\begin{itemize}
\item Creating good logic-level representation of arithmetic functions. \\
This also means using dedicated hardware resources such as half- and full-adder
cells in ASICS or dedicated carry logic in FPGAs.
\smallskip
\item Mapping of coarse-grain resources such as block memory or DSP cells.
\end{itemize}
\end{itemize}
\end{frame}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\subsection{Coarse-grain synthesis}

\begin{frame}
\subsectionpage
\subsectionpagesuffix
\end{frame}

\subsubsection{Intro to coarse-grain synthesis}

\begin{frame}[fragile]{\subsubsecname}
In coarse-grain synthesis the target architecure has cells of the same
complexity or larger complexity than the internal RTL representation.

For example:
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]
	wire [15:0] a, b;
	wire [31:0] c, y;
	assign y = a * b + c;
\end{lstlisting}

This circuit contains two cells in the RTL representation: one multiplier and
one adder.

\medskip
Coarse grain synthesis is mapping this circuit to a single multiply-add cell
of the target architecture, for example using an FPGA DSP core.

\bigskip
Fine-grain synthesis would be matching the circuit to smaller elements, such
as LUTs, gates, or half- and full-adders.
\end{frame}

\subsubsection{The extract pass}

\begin{frame}{\subsubsecname}
\begin{itemize}
\item Like the {\tt techmap} pass, the {\tt extract} pass is called with
a map file. It compares the circuits inside the modules of the map file
with the design and looks for sub-circuits in the design that match any
of the modules in the map file.
\bigskip
\item If a match is found, the {\tt extract} pass will replace the matching
subcircuit with an instance of the module from the map file.
\bigskip
\item In a way the {\tt extract} pass is the inverse of the techmap pass.
\end{itemize}
\end{frame}

\begin{frame}[t, fragile]{\subsubsecname{} -- Example 1/2}
\vbox to 0cm{
\vskip2cm
\begin{tikzpicture}
    \node at (0,0) {\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00a.pdf}};
    \node at (3,-3) {\includegraphics[width=8cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00b.pdf}};
    \draw[yshift=0.2cm,thick,-latex] (1,-1) -- (2,-2);
\end{tikzpicture}
\vss}
\vskip-1.2cm
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/macc_simple_xmap.v}
\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys]
read_verilog macc_simple_test.v
hierarchy -check -top test

extract -map macc_simple_xmap.v;;
\end{lstlisting}
\end{columns}
\end{frame}

\begin{frame}[fragile]{\subsubsecname{} -- Example 2/2}
\hfil\begin{tabular}{cc}
\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_01.v}}} &
\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_02.v}}} \\
$\downarrow$ & $\downarrow$ \\
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01a.pdf}} &
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02a.pdf}} \\
$\downarrow$ & $\downarrow$ \\
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01b.pdf}} &
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02b.pdf}} \\
\end{tabular}
\end{frame}

\subsubsection{The wrap-extract-unwrap method}

\begin{frame}{\subsubsecname}
TBD
\end{frame}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\subsection{Automatic design changes}

\begin{frame}
\subsectionpage
\subsectionpagesuffix
\end{frame}

\subsubsection{TBD}

\begin{frame}{\subsubsecname}
TBD
\end{frame}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\subsection{Summary}

\begin{frame}{\subsecname}
\begin{itemize}
\item TBD
\item TBD
\item TBD
\item TBD
\end{itemize}

\bigskip
\bigskip
\begin{center}
Questions?
\end{center}

\bigskip
\bigskip
\begin{center}
\url{http://www.clifford.at/yosys/}
\end{center}
\end{frame}