manual/PRESENTATION_ExSyn/memory_01.v


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module test(input      CLK, ADDR,
            input      [7:0] DIN,
	    output reg [7:0] DOUT);
    reg [7:0] mem [0:1];
    always @(posedge CLK) begin
        mem[ADDR] <= DIN;
	DOUT <= mem[ADDR];
    end
endmodule