blob: 68fe0308e7616e675396da7fa78eb3469c1630ff (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
|
# read design
read_verilog counter.v
hierarchy -check -top counter
show -format pdf -prefix counter_00
# the high-level stuff
proc; opt; memory; opt; fsm; opt
show -format pdf -prefix counter_01
# mapping to internal cell library
techmap; splitnets -ports; opt
show -format pdf -prefix counter_02
# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
# mapping logic to mycells.lib
abc -liberty mycells.lib
# cleanup
clean
show -lib mycells.v -format pdf -prefix counter_03
|
