1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
struct DeleteWireWorker
{
RTLIL::Module *module;
std::set<std::string> *delete_wires_p;
void operator()(RTLIL::SigSpec &sig) {
sig.optimize();
for (auto &c : sig.chunks)
if (c.wire != NULL && delete_wires_p->count(c.wire->name))
c.wire = module->new_wire(c.width, NEW_ID);
}
};
struct DeletePass : public Pass {
DeletePass() : Pass("delete", "delete objects in the design") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" delete [selection]\n");
log("\n");
log("Deletes the selected objects. This will also remove entire modules, if the\n");
log("whole module is selected.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
// if (arg[argidx] == "-something") {
// flag_something = true;
// continue;
// }
break;
}
extra_args(args, argidx, design);
std::vector<std::string> delete_mods;
for (auto &mod_it : design->modules)
{
if (design->selected_whole_module(mod_it.first)) {
delete_mods.push_back(mod_it.first);
continue;
}
if (!design->selected_module(mod_it.first))
continue;
RTLIL::Module *module = mod_it.second;
std::set<std::string> delete_wires;
std::set<std::string> delete_cells;
std::set<std::string> delete_procs;
std::set<std::string> delete_mems;
for (auto &it : module->wires)
if (design->selected(module, it.second))
delete_wires.insert(it.first);
for (auto &it : module->memories)
if (design->selected(module, it.second))
delete_mems.insert(it.first);
for (auto &it : module->cells) {
if (design->selected(module, it.second))
delete_cells.insert(it.first);
if ((it.second->type == "$memrd" || it.second->type == "$memwr") &&
delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0)
delete_cells.insert(it.first);
}
for (auto &it : module->processes)
if (design->selected(module, it.second))
delete_procs.insert(it.first);
DeleteWireWorker delete_wire_worker;
delete_wire_worker.module = module;
delete_wire_worker.delete_wires_p = &delete_wires;
module->rewrite_sigspecs(delete_wire_worker);
for (auto &it : delete_wires) {
delete module->wires.at(it);
module->wires.erase(it);
}
for (auto &it : delete_mems) {
delete module->memories.at(it);
module->memories.erase(it);
}
for (auto &it : delete_cells) {
delete module->cells.at(it);
module->cells.erase(it);
}
for (auto &it : delete_procs) {
delete module->processes.at(it);
module->processes.erase(it);
}
module->fixup_ports();
}
for (auto &it : delete_mods) {
delete design->modules.at(it);
design->modules.erase(it);
}
}
} DeletePass;
|
