blob: 5e71c468f0b21d2edc4265b82b2c53af8bc31569 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
|
bram $__XILINX_RAMB36_SDP
init 1
abits 9
dbits 72
groups 2
ports 1 1
wrmode 0 1
enable 0 8
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB18_SDP
init 1
abits 9
dbits 36
groups 2
ports 1 1
wrmode 0 1
enable 0 4
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB36_TDP
init 1
abits 10 @a10d36
dbits 36 @a10d36
abits 11 @a11d18
dbits 18 @a11d18
abits 12 @a12d9
dbits 9 @a12d9
abits 13 @a13d4
dbits 4 @a13d4
abits 14 @a14d2
dbits 2 @a14d2
abits 15 @a15d1
dbits 1 @a15d1
groups 2
ports 1 1
wrmode 0 1
enable 0 4 @a10d36
enable 0 2 @a11d18
enable 0 1 @a12d9 @a13d4 @a14d2 @a15d1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB18_TDP
init 1
abits 10 @a10d18
dbits 18 @a10d18
abits 11 @a11d9
dbits 9 @a11d9
abits 12 @a12d4
dbits 4 @a12d4
abits 13 @a13d2
dbits 2 @a13d2
abits 14 @a14d1
dbits 1 @a14d1
groups 2
ports 1 1
wrmode 0 1
enable 0 2 @a10d18
enable 0 1 @a11d9 @a12d4 @a13d2 @a14d1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
match $__XILINX_RAMB36_SDP
min bits 4096
min efficiency 5
shuffle_enable B
make_transp
or_next_if_better
endmatch
match $__XILINX_RAMB18_SDP
min bits 4096
min efficiency 5
shuffle_enable B
make_transp
or_next_if_better
endmatch
match $__XILINX_RAMB36_TDP
min bits 4096
min efficiency 5
shuffle_enable B
make_transp
or_next_if_better
endmatch
match $__XILINX_RAMB18_TDP
min bits 4096
min efficiency 5
shuffle_enable B
make_transp
endmatch
|
