blob: a156082f43fab3c76ed9b1cea2312b37a81e32fa (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
|
//-----------------------------------------------------
// Design Name : dff_async_reset
// File Name : dff_async_reset.v
// Function : D flip-flop async reset
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module dff_async_reset (
data , // Data Input
clk , // Clock Input
reset , // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset ;
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------Code Starts Here---------
always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule //End Of Module dff_async_reset
|
