blob: 6acf243fd41a5d96b98bf93fb4148802982f293a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
|
//-----------------------------------------------------
// Design Name : half_adder_gates
// File Name : half_adder_gates.v
// Function : CCITT Serial CRC
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module half_adder_gates(x,y,sum,carry);
input x,y;
output sum,carry;
and U_carry (carry,x,y);
xor U_sum (sum,x,y);
endmodule
|
