tests/asicworld/code_verilog_tutorial_flip_flop.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

module flif_flop (clk,reset, q, d);
input clk, reset, d;
output q;
reg q;
  	  	 
always @ (posedge clk )
begin
  if (reset == 1) begin
    q <= 0;
  end else begin
    q <= d;
  end
end
  	  	 
endmodule