blob: eb21315d779c717f01cf0acafdf83d172858d57f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
|
module test(in, out, vin, vout, vin1, vout1, vin2, vout2);
input in;
input [3:0] vin, vin1, vin2;
output [3:0] vout, vout1, vout2;
output out;
assign out = in << 1;
assign vout = vin << 2;
assign vout1 = vin1 >> 2;
assign vout2 = vin2 >>> 2;
endmodule
|
