blob: eba4e88eab01534899637428de76da8db798ad77 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
|
// test_simulation_seq_ff_1_test.v
module f1_test(input in, input clk, output reg out);
always @(posedge clk)
out <= in;
endmodule
// test_simulation_seq_ff_2_test.v
module f2_test(input in, input clk, output reg out);
always @(negedge clk)
out <= in;
endmodule
|
