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module top_properties (input logic clock, read, write, ready);
a_rw: assert property ( @(posedge clock) !(read && write) );
`ifdef FAIL
a_wr: assert property ( @(posedge clock) write |-> ready );
`else
a_wr: assert property ( @(posedge clock) write |=> ready );
`endif
endmodule
bind top top_properties properties_inst (.*);
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