diff options
Diffstat (limited to 'doc/man/ext2sim.1')
| -rw-r--r-- | doc/man/ext2sim.1 | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/doc/man/ext2sim.1 b/doc/man/ext2sim.1 index 98e8381..c03803d 100644 --- a/doc/man/ext2sim.1 +++ b/doc/man/ext2sim.1 @@ -74,7 +74,7 @@ Don't output transistor or node attributes in the \fB.sim\fR file. This option will also disable the output of information such as the area and perimeter of source and drain diffusion and the fet substrate. For compatibitlity reasons the latest version of ext2sim -outputs this information as node attibutes. +outputs this information as node attributes. This option is necessary when preparing input for programs that don't know about attributes, such as \fIsim2spice\fR\|(1) (which is actually made obsolete by \fIext2spice\fR\|(1), anyway), @@ -101,7 +101,7 @@ SU is the internal Stanford format which is described also in \fIsim\fR(5) and includes areas and perimeters of fet sources, drains and substrates. .TP 1.0i .B \-y \fInum\fR -Select the precision for outputing capacitors. The default is 1 which means +Select the precision for outputting capacitors. The default is 1 which means that the capacitors will be printed to a precision of .1 fF. .TP 1.0i .B \-J \fIhier|flat\fR @@ -120,7 +120,7 @@ individually control how a terminal of a specific fet will be extracted if you put a source/drain attribute. \fIext:aph\fR makes the extraction for that specific terminal hierarchical and \fIext:apf\fR makes the extraction flat (see the magic tutorial about attaching attribute labels). -Additionaly to ease extraction of bipolar transistors the gate attribute +Additionally to ease extraction of bipolar transistors the gate attribute \fIext:aps\fR forces the output of the substrate area and perimeter for a specific fet (in flat mode only). .TP 1.0i @@ -145,7 +145,7 @@ pump). To get the correct substrate info in these cases the fet(s) with separate wells should be in their own separate subcell with ext:aph attributes attached to their sensitive terminals (also all the transistors which share -sensistive terminals with these should be in another subcell with the same +sensitive terminals with these should be in another subcell with the same attributes). @@ -177,7 +177,7 @@ capacitances, as most analysis tools compute the gate capacitance directly from the gate area. The \fB-c\fR flag therefore provides a limit only on non-gate capacitance. The areas and perimeters of fet sources and drains work only with the -simple extraction algorith and not with the extresis flow. So you have +simple extraction algorithm and not with the extresis flow. So you have to model them as linear capacitors (create a special extraction style) if you want to extract parasitic resistances with extresis. |