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-rw-r--r--data/mcus.xml103
1 files changed, 74 insertions, 29 deletions
diff --git a/data/mcus.xml b/data/mcus.xml
index 3c75a4a..4755c75 100644
--- a/data/mcus.xml
+++ b/data/mcus.xml
@@ -11,22 +11,22 @@
<!-- MCU definition tag -->
<!ELEMENT mcu (timers, more, bits, writeonly, sfr)>
-
+
<!-- Detailed specification of MCU parameters (all of them must not be an empty string)
vendor - Vendor name
name - Processor type
xdata - External data memory connectable
- xcode - External program memoryconnectable
+ xcode - External program memoryconnectable
code - Capacity of internal program memory in kilo bytes (not bytes !)
frequency - Operating oscilator frequency (e.g "0 to 24 MHz")
ram - Capacity of internal data memory in bytes
portbits - Number of IO lines
- uart - UART avaliable
+ uart - UART available
interrupts - Number of interrupts
voltage - Oprating voltage (e.g "2.7 to 5.5 V")
- timer2 - Timer 2 avaliable
- watchdog - Watchdog timer avaliable
- eram - Size of ERAM (0 means no eram avaliable) (> 0 requires intelpe="no")
+ timer2 - Timer 2 available
+ watchdog - Watchdog timer available
+ eram - Size of ERAM (0 means no eram available) (> 0 requires intelpe="no")
dualdtpr - Dual Data Pointer (includes register AUXR1 if wdtcon="no")
auxr - Register AUXR
t2mod - Register T2MOD
@@ -34,14 +34,14 @@
0 - Bit not implemented
1 - Bit implemented
e.g. port0="11110011" means:
- P0.0 - implemented
- P0.1 - implemented
- P0.2 - implemented
- P0.3 - implemented
- P0.4 - not implemented
- P0.5 - not implemented
- P0.6 - implemented
- P0.7 - implemented
+ P0.0 - implemented
+ P0.1 - implemented
+ P0.2 - implemented
+ P0.3 - implemented
+ P0.4 - not implemented
+ P0.5 - not implemented
+ P0.6 - implemented
+ P0.7 - implemented
pof - Power Off Flag implemented
gf0 - PCON.3 (General purpose flag) implemented
gf1 - PCON.4 (General purpose flag) implemented
@@ -132,12 +132,12 @@
<!-- Hexadecimal addresses of write only registers (e.g. AF 85 4B) -->
<!ELEMENT writeonly (#PCDATA)>
-
- <!-- List of SFR and SFB which are avaliable on the choosen MCU
+
+ <!-- List of SFR and SFB which are available on the choosen MCU
Implicit SFR and SFB:
B ACC A TMOD TH0 TH1 SP DPL DPH PCON
TL0 TL1 AB
-
+
PSW C CY AC F0 RS1 RS0 OV P
IE EA ET1 EX1 ET0 EX0
IP PT1 PX1 PT0 PX0
@@ -145,7 +145,7 @@
-->
<!ELEMENT sfr (#PCDATA)>
]>
-<mcus lastupdate="02/10/09">
+<mcus lastupdate="11/02/11">
<mcu
vendor="Intel" name="8051"
xdata="yes" xcode="yes"
@@ -384,7 +384,7 @@
</writeonly><sfr>
P0 P1 P2 P3 SBUF ES PS ET2 PT2
RCAP2L RCAP2H TL2 TH2
-
+
SCON SM0 SM1 SM2 REN TB8 RB8 TI RI
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2
</sfr>
@@ -422,7 +422,7 @@
</writeonly><sfr>
P0 P1 P2 P3 SBUF ES PS ET2 PT2
RCAP2L RCAP2H TL2 TH2
-
+
SCON SM0 SM1 SM2 REN TB8 RB8 TI RI
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2
</sfr>
@@ -460,7 +460,7 @@
</writeonly><sfr>
P0 P1 P2 P3 SBUF ES PS ET2 PT2
RCAP2L RCAP2H TL2 TH2
-
+
SCON SM0 SM1 SM2 REN TB8 RB8 TI RI
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2
</sfr>
@@ -505,9 +505,9 @@
C903 B83F A8BF 878F
</bits><writeonly>
</writeonly><sfr>
- P0 P1 P2 P3 SBUF ES PS ET2 PT2
+ P0 P1 P2 P3 SBUF ES PS ET2 PT2
SADEN SADDR RCAP2L RCAP2H TL2 TH2 T2MOD IPH FE
-
+
SCON SM0 SM1 SM2 REN TB8 RB8 TI RI
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2
</sfr>
@@ -554,7 +554,7 @@
</writeonly><sfr>
P0 P1 P2 P3 SBUF ES PS ET2 PT2
SADEN SADDR RCAP2L RCAP2H TL2 TH2 T2MOD IPH FE
-
+
SCON SM0 SM1 SM2 REN TB8 RB8 TI RI
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2
</sfr>
@@ -601,7 +601,7 @@
</writeonly><sfr>
P0 P1 P2 P3 SBUF ES PS ET2 PT2
SADEN SADDR RCAP2L RCAP2H TL2 TH2 T2MOD IPH FE
-
+
SCON SM0 SM1 SM2 REN TB8 RB8 TI RI
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2
</sfr>
@@ -648,7 +648,7 @@
</writeonly><sfr>
P0 P1 P2 P3 SBUF ES PS ET2 PT2
SADEN SADDR RCAP2L RCAP2H TL2 TH2 T2MOD IPH FE
-
+
SCON SM0 SM1 SM2 REN TB8 RB8 TI RI
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2
</sfr>
@@ -695,7 +695,7 @@
</writeonly><sfr>
P0 P1 P2 P3 SBUF ES PS ET2 PT2
SADEN SADDR RCAP2L RCAP2H TL2 TH2 T2MOD IPH FE
-
+
SCON SM0 SM1 SM2 REN TB8 RB8 TI RI
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2
</sfr>
@@ -742,7 +742,7 @@
</writeonly><sfr>
P0 P1 P2 P3 SBUF ES PS ET2 PT2
SADEN SADDR RCAP2L RCAP2H TL2 TH2 T2MOD IPH FE
-
+
SCON SM0 SM1 SM2 REN TB8 RB8 TI RI
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2
</sfr>
@@ -789,7 +789,7 @@
</writeonly><sfr>
P0 P1 P2 P3 SBUF ES PS ET2 PT2
SADEN SADDR RCAP2L RCAP2H TL2 TH2 T2MOD IPH FE
-
+
SCON SM0 SM1 SM2 REN TB8 RB8 TI RI
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2
</sfr>
@@ -1136,6 +1136,51 @@
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2
</sfr>
</mcu><mcu
+ vendor="Atmel" name="AT89S51"
+ xdata="yes" xcode="yes"
+ code="4" frequency="0 to 33 MHz"
+ ram="128" portbits="32"
+ uart="yes" interrupts="6"
+ voltage="4.0 to 5.5" timer2="no"
+ watchdog="yes" eram="0"
+ dualdtpr="yes" auxr="yes"
+ t2mod="no" port0="11111111"
+ port1="11111111" port2="11111111"
+ port3="11111111" port4=""
+ pof="yes" gf0="yes"
+ gf1="yes" pd="no"
+ idl="no" smod0="no"
+ iph="no" acomparator="no"
+ euart="no" clkreg="no"
+ pwdex="no" spi="no"
+ wdtcon="no" eeprom="0"
+ intelpe="no" pwm="no"
+ x2reset="no" ckcon="no"
+ auxr1gf3="no" ao="no"
+ wdtprg="no" hddptr="no"
+ auxrwdidle="yes" auxrdisrto="yes">
+ <timers>Two 16-bit</timers>
+ <more>
+ Three-level Program Memory Lock
+ Low-power Idle and Power-down Modes
+ Interrupt Recovery from Power-down Mode
+ Watchdog Timer
+ Dual Data Pointer
+ Power-off Flag
+ Fast Programming Time
+ Flexible ISP Programming (Byte and Page Mode)
+ </more><bits>
+ B83F A8BF A201 8E19 878F
+ </bits><writeonly>
+ A6
+ </writeonly><sfr>
+ P0 P1 P2 P3 SBUF
+ T2MOD AUXR AUXR1 WDTRST
+ DP0H DP0L DP1H DP1L
+ SCON SM0 SM1 SM2 REN TB8 RB8 TI RI
+ T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2
+ </sfr>
+ </mcu><mcu
vendor="Atmel" name="AT89S52"
xdata="yes" xcode="yes"
code="8" frequency="0 to 33 MHz"
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-26 21:32:28 +0000