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| author | Tim Edwards <tim@opencircuitdesign.com> | 2015-11-11 11:31:09 -0500 |
|---|---|---|
| committer | Tim Edwards <tim@opencircuitdesign.com> | 2015-11-11 11:31:09 -0500 |
| commit | 821ffe465d900fda969ef2025cbfd815c1310023 (patch) | |
| tree | afe0fe1d7d05981a04e9f413c1513ad89f5da303 /scripts/synthesize.sh | |
| parent | 9e91a9d0bca51a8d35e6784244b3d636634117de (diff) | |
Corrected synthesis script, which had added the line necessary to
process RTL in the verilog source, but only added it to the
preliminary yosys script, not to the final one.
Diffstat (limited to 'scripts/synthesize.sh')
| -rwxr-xr-x | scripts/synthesize.sh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/scripts/synthesize.sh b/scripts/synthesize.sh index ec59dd3..526c6ff 100755 --- a/scripts/synthesize.sh +++ b/scripts/synthesize.sh @@ -197,6 +197,7 @@ EOF endif cat > ${rootname}.ys << EOF +read_liberty -lib -ignore_miss_dir -setattr blackbox ${libertypath} read_verilog ${rootname}.v EOF |