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| author | Tim Edwards <tim@opencircuitdesign.com> | 2015-05-29 11:03:29 -0400 |
|---|---|---|
| committer | Tim Edwards <tim@opencircuitdesign.com> | 2015-05-29 11:03:29 -0400 |
| commit | 8b22c1da637f67f1014a682ae48a2122c98b824c (patch) | |
| tree | cef6fc0e4741b9b6887cf38cf72feeea3cb64b57 /scripts/synthesize.sh | |
| parent | 5a694037e2a33cdbfa013fc7a2d75c546c500fd3 (diff) | |
Added a new option to "project_vars.sh" called "yosys_nodebug".
If set to 1, the yosys script uses "clean -purge" after the
standard cell mapping. This removes all the buffers that are
used to maintain internal signal names, resulting in a smaller
but less easily debugged layout.
Diffstat (limited to 'scripts/synthesize.sh')
| -rwxr-xr-x | scripts/synthesize.sh | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/scripts/synthesize.sh b/scripts/synthesize.sh index 7b8999d..d05dabe 100755 --- a/scripts/synthesize.sh +++ b/scripts/synthesize.sh @@ -224,6 +224,14 @@ abc -liberty ${techdir}/${libertyfile} flatten EOF +# Purge buffering of internal net name aliases for a smaller, +# non-debug output +if ( ${?yosys_nodebug} ) then + cat >> ${rootname}.ys << EOF +clean -purge +EOF +endif + # Map tiehi and tielo, if they are defined if ( ${?tiehi} && ${?tiehipin_out} ) then |