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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-05 01:59:30 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-05 01:59:30 +0100 |
| commit | 078cecf9eaa234b868ec3a30b281217a00418d61 (patch) | |
| tree | 1e4864fb3e42b729df0f57f6b38875fdf331da0e | |
| parent | aa9da46807af24d906af371ba9c4ee9b7430f82c (diff) | |
Updated todo items in README file
| -rw-r--r-- | README | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -308,8 +308,7 @@ Roadmap / Large-scale TODOs - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.) - Implement SAT-based formal equivialence checker - - Rewrite freduce pass with input-cone analysis - - Write equiv pass, base hypothesis on input cones + - Write equiv pass based on hint-based register mapping - Re-implement Verilog frontend (far future) - cleaner (easier to use, harder to use wrong) AST format @@ -323,6 +322,7 @@ Other Unsorted TODOs - Implement missing Verilog 2005 features: - Multi-dimensional arrays + - Support for real (float) const. expressions and parameters - ROM modeling using $readmemh/$readmemb in "initial" blocks - Ignore what needs to be ignored (e.g. drive and charge strengths) - Check standard vs. implementation to identify missing features |