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authorClifford Wolf <clifford@clifford.at>2015-01-31 23:25:32 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-31 23:25:32 +0100
commit8dfa105255be4fd84a39df6c4913b5ff3cc1dc80 (patch)
treefe4282d57c63c6a8fd021df65de23c7790a1222b
parent67218443becc134d552b16a98b87f0cb2318c23d (diff)
Bugfix in opt_const $eq -> buffer code
-rw-r--r--passes/opt/opt_const.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 6a830dd0..55da987a 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -524,11 +524,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
- if (a.is_fully_const()) {
+ if (a.is_fully_const() && !b.is_fully_const()) {
cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type.str());
- RTLIL::SigSpec tmp = cell->getPort("\\A");
- cell->setPort("\\A", cell->getPort("\\B"));
- cell->setPort("\\B", tmp);
+ cell->setPort("\\A", b);
+ cell->setPort("\\B", a);
+ std::swap(a, b);
}
if (b.is_fully_const()) {