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authorClifford Wolf <clifford@clifford.at>2015-01-02 13:59:47 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-02 13:59:47 +0100
commitbbf89c4dc68475b57709897ab0728e31963a1ddb (patch)
treeeabe436692079854cf4bcd3ab00dea0ca63feb85
parent36c20f2ede51580f7c68b96b9cde9473187a8fc6 (diff)
Progress in memory_bram
-rw-r--r--Makefile1
-rw-r--r--passes/memory/memory_bram.cc9
-rw-r--r--tests/bram/generate.py17
-rw-r--r--tests/bram/run-single.sh5
-rwxr-xr-xtests/bram/run-test.sh2
5 files changed, 18 insertions, 16 deletions
diff --git a/Makefile b/Makefile
index 73514e52..38e89213 100644
--- a/Makefile
+++ b/Makefile
@@ -264,6 +264,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
+cd tests/fsm && bash run-test.sh
+cd tests/techmap && bash run-test.sh
+cd tests/memories && bash run-test.sh
+ +cd tests/bram && bash run-test.sh
+cd tests/various && bash run-test.sh
+cd tests/sat && bash run-test.sh
@echo ""
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 853950a3..1f7436d2 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -306,10 +306,10 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
SigBit last_en_bit = State::S1;
for (int i = 0; i < mem_width; i++) {
if (pi.enable && i % (bram.dbits / pi.enable) == 0) {
- last_en_bit = wr_en[i];
+ last_en_bit = wr_en[i + cell_port_i*mem_width];
sig_en.append(last_en_bit);
}
- if (last_en_bit != wr_en[i]) {
+ if (last_en_bit != wr_en[i + cell_port_i*mem_width]) {
log(" Bram port %c%d has incompatible enable structure.\n", pi.group + 'A', pi.index + 1);
goto skip_bram_wport;
}
@@ -328,6 +328,7 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
pi.sig_addr = wr_addr.extract(cell_port_i*mem_abits, mem_abits);
pi.sig_data = wr_data.extract(cell_port_i*mem_width, mem_width);
+ bram_port_i++;
goto mapped_wr_port;
}
@@ -338,6 +339,7 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
int grow_read_ports_cursor = -1;
bool try_growing_more_read_ports = false;
+ auto backup_clock_domains = clock_domains;
if (0) {
grow_read_ports:;
@@ -360,6 +362,7 @@ grow_read_ports:;
}
try_growing_more_read_ports = false;
portinfos.swap(new_portinfos);
+ clock_domains = backup_clock_domains;
dup_count++;
}
@@ -448,7 +451,7 @@ grow_read_ports:;
string prefix = stringf("%c%d", pi.group + 'A', pi.index + 1);
const char *pf = prefix.c_str();
- if (pi.clocks)
+ if (pi.clocks && (!clocks.count(pi.clocks) || pi.sig_clock.wire))
clocks[pi.clocks] = pi.sig_clock;
SigSpec addr_ok;
diff --git a/tests/bram/generate.py b/tests/bram/generate.py
index 37b23a52..b03d1529 100644
--- a/tests/bram/generate.py
+++ b/tests/bram/generate.py
@@ -15,10 +15,6 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
dbits = random.randrange(1, 8)
groups = random.randrange(1, 5)
- # XXX
- init = 0
- groups = 2
-
if random.randrange(2):
abits = 2 ** random.randrange(1, 4)
if random.randrange(2):
@@ -32,12 +28,10 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
clkpol = [ random.randrange(4) for i in range(groups) ]
# XXX
- ports = [ 1 for i in range(groups) ]
- wrmode = [ 1 for i in range(groups) ]
+ init = 0
transp = [ 0 for i in range(groups) ]
clocks = [ 1 for i in range(groups) ]
clkpol = [ 1 for i in range(groups) ]
- wrmode[0] = 0
for p1 in range(groups):
if wrmode[p1] == 0:
@@ -187,7 +181,7 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
if debug_mode:
print(" $dumpfile(`vcd_file);", file=tb_f)
- print(" $dumpvars(2, bram_%02d_%02d_tb);" % (k1, k2), file=tb_f)
+ print(" $dumpvars(0, bram_%02d_%02d_tb);" % (k1, k2), file=tb_f)
for p in (tb_clocks + tb_addr + tb_din):
if p[-2:] == "EN":
@@ -205,13 +199,14 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
if len(tb_clocks):
c = random.choice(tb_clocks)
print(" %s = !%s;" % (c, c), file=tb_f)
+ print(" #100;", file=tb_f)
+ print(" $display(\"bram_%02d_%02d %3d: %%b %%b %%s\", %s, %s, error ? \"ERROR\" : \"OK\");" %
+ (k1, k2, i, expr_dout, expr_dout_ref), file=tb_f)
for p in tb_din:
print(" %s <= %d;" % (p, random.randrange(1048576)), file=tb_f)
for p in tb_addr:
print(" %s <= %d;" % (p, random.choice(tb_addrlist)), file=tb_f)
- print(" #1000;", file=tb_f)
- print(" $display(\"bram_%02d_%02d %3d: %%b %%b %%s\", %s, %s, error ? \"ERROR\" : \"OK\");" %
- (k1, k2, i, expr_dout, expr_dout_ref), file=tb_f)
+ print(" #900;", file=tb_f)
print(" end", file=tb_f)
print("endmodule", file=tb_f)
diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh
index 254e8518..8a022e59 100644
--- a/tests/bram/run-single.sh
+++ b/tests/bram/run-single.sh
@@ -5,5 +5,8 @@ set -e
iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v temp/brams_${1}_ref.v \
temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v
temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt
-if grep -H -C1 ERROR temp/tb_${1}_${2}.txt; then exit 1; fi
+if grep -q ERROR temp/tb_${1}_${2}.txt; then
+ grep -HC2 ERROR temp/tb_${1}_${2}.txt | head
+ exit 1
+fi
exit 0
diff --git a/tests/bram/run-test.sh b/tests/bram/run-test.sh
index 68523740..cdf7d61b 100755
--- a/tests/bram/run-test.sh
+++ b/tests/bram/run-test.sh
@@ -21,7 +21,7 @@ python generate.py
for j in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' | grep -v $i ); do
echo "temp/job_${i}_${j}.ok:"
echo " @bash run-single.sh ${i} ${j}"
- echo " @echo 'Passed test ${i}_${j}.'"
+ echo " @echo 'Passed memory_bram test ${i}_${j}.'"
echo " @touch \$@"
done; done
} > temp/makefile