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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-20 11:05:58 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-20 11:05:58 +0100 |
| commit | ac2be2d892e3311b89744306e8c29445f588f590 (patch) | |
| tree | 10c83aaca2c434c7abd9875f285e3a67a707e365 /README | |
| parent | 19dba2561ece488543e1728ba800386943abb77c (diff) | |
Fixed name resolution of local tasks and functions in generate block
Diffstat (limited to 'README')
| -rw-r--r-- | README | 1 |
1 files changed, 0 insertions, 1 deletions
@@ -292,7 +292,6 @@ Roadmap / Large-scale TODOs - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim - Missing Verilog-2005 features to be implemented soon: - - Fix corner cases with contextual name lookup - Indexed part selects - Technology mapping for real-world applications |