diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-11-22 15:01:12 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-22 15:01:12 +0100 |
| commit | 295e352ba6aa1bd71431abc21a8f93735968cae6 (patch) | |
| tree | 2261f6a66d6fa1e7f67d2aa220f6e4f588be4cea /backends/spice | |
| parent | c854ad2e7ecae6115182e9210f2b6c57afa98c23 (diff) | |
Renamed "placeholder" to "blackbox"
Diffstat (limited to 'backends/spice')
| -rw-r--r-- | backends/spice/spice.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index e1a196b8..6c8a3ec9 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -57,7 +57,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de if (design->modules.count(cell->type) == 0) { - log("Warning: no (placeholder) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n", + log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n", RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name)); for (auto &conn : cell->connections) { RTLIL::SigSpec sig = sigmap(conn.second); @@ -178,7 +178,7 @@ struct SpiceBackend : public Backend { for (auto module_it : design->modules) { RTLIL::Module *module = module_it.second; - if (module->get_bool_attribute("\\placeholder")) + if (module->get_bool_attribute("\\blackbox")) continue; if (module->processes.size() != 0) |