diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-08-16 18:18:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-16 18:29:39 +0200 |
| commit | 47c2637a961839f1eb1a0386f7e54d94be50bc10 (patch) | |
| tree | 2db3bfbabf1ad7ca21176c2639b565720655fb8b /backends/verilog/verilog_backend.cc | |
| parent | 56a30cf42c6a40f265a67df6e2c5fa74657fbf5b (diff) | |
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 44 |
1 files changed, 40 insertions, 4 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 81c938bd..0fcd60cd 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -381,21 +381,25 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") { + if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_")) { fprintf(f, "%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); fprintf(f, " = "); + if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_")) + fprintf(f, "~("); dump_cell_expr_port(f, cell, "A", false); fprintf(f, " "); - if (cell->type == "$_AND_") + if (cell->type.in("$_AND_", "$_NAND_")) fprintf(f, "&"); - if (cell->type == "$_OR_") + if (cell->type.in("$_OR_", "$_NOR_")) fprintf(f, "|"); - if (cell->type == "$_XOR_") + if (cell->type.in("$_XOR_", "$_XNOR_")) fprintf(f, "^"); dump_attributes(f, "", cell->attributes, ' '); fprintf(f, " "); dump_cell_expr_port(f, cell, "B", false); + if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_")) + fprintf(f, ")"); fprintf(f, ";\n"); return true; } @@ -414,6 +418,38 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type.in("$_AOI3_", "$_OAI3_")) { + fprintf(f, "%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + fprintf(f, " = ("); + dump_cell_expr_port(f, cell, "A", false); + fprintf(f, cell->type == "$_AOI3_" ? " & " : " | "); + dump_cell_expr_port(f, cell, "B", false); + fprintf(f, cell->type == "$_AOI3_" ? ") |" : ") &"); + dump_attributes(f, "", cell->attributes, ' '); + fprintf(f, " "); + dump_cell_expr_port(f, cell, "C", false); + fprintf(f, ";\n"); + return true; + } + + if (cell->type.in("$_AOI4_", "$_OAI4_")) { + fprintf(f, "%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + fprintf(f, " = ("); + dump_cell_expr_port(f, cell, "A", false); + fprintf(f, cell->type == "$_AOI4_" ? " & " : " | "); + dump_cell_expr_port(f, cell, "B", false); + fprintf(f, cell->type == "$_AOI4_" ? ") |" : ") &"); + dump_attributes(f, "", cell->attributes, ' '); + fprintf(f, " ("); + dump_cell_expr_port(f, cell, "C", false); + fprintf(f, cell->type == "$_AOI4_" ? " & " : " | "); + dump_cell_expr_port(f, cell, "D", false); + fprintf(f, ");\n"); + return true; + } + if (cell->type.substr(0, 6) == "$_DFF_") { std::string reg_name = cellname(cell); |