diff options
| author | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-01-03 10:54:54 +0100 |
|---|---|---|
| committer | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-01-03 10:54:54 +0100 |
| commit | 06482c046bcab4e2b9603f8954ce0f2fd501a73b (patch) | |
| tree | d160ad05402768e4f468ff0685593b81658e6a5a /backends | |
| parent | 5da334fc2efd66c8a5efde925bb18212c34d0cef (diff) | |
| parent | fb2bf934dc6d2c969906b350c9a1b09a972bfdd7 (diff) | |
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/ilang/ilang_backend.cc | 2 | ||||
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 14 |
2 files changed, 9 insertions, 7 deletions
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index 66775b2a..924e316b 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -402,7 +402,7 @@ struct DumpPass : public Pass { log("ilang format.\n"); log("\n"); log(" -m\n"); - log(" also dump the module headers, even if only parts of a single"); + log(" also dump the module headers, even if only parts of a single\n"); log(" module is selected\n"); log("\n"); log(" -n\n"); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index ff41c2e3..d8160c97 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -506,12 +506,14 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) HANDLE_BINOP("$sshl", "<<<") HANDLE_BINOP("$sshr", ">>>") - HANDLE_BINOP("$lt", "<") - HANDLE_BINOP("$le", "<=") - HANDLE_BINOP("$eq", "==") - HANDLE_BINOP("$ne", "!=") - HANDLE_BINOP("$ge", ">=") - HANDLE_BINOP("$gt", ">") + HANDLE_BINOP("$lt", "<") + HANDLE_BINOP("$le", "<=") + HANDLE_BINOP("$eq", "==") + HANDLE_BINOP("$ne", "!=") + HANDLE_BINOP("$eqx", "===") + HANDLE_BINOP("$nex", "!==") + HANDLE_BINOP("$ge", ">=") + HANDLE_BINOP("$gt", ">") HANDLE_BINOP("$add", "+") HANDLE_BINOP("$sub", "-") |