Some spelling errors fixed

Gbp-Pq: Name 0009-Some-spelling-errors-fixed.patch

1 files changed, 1 insertions, 1 deletions

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index a617215f..6f03f25e 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1253,7 +1253,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 	active_module = module;
 
 	if (!module->processes.empty())
-		log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n"
+		log_warning("Module %s contains unmapped RTLIL processes. RTLIL processes\n"
 				"can't always be mapped directly to Verilog always blocks. Unintended\n"
 				"changes in simulation behavior are possible! Use \"proc\" to convert\n"
 				"processes to logic networks and registers.", log_id(module));