diff options
| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2015-08-14 13:23:01 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-08-14 23:27:05 +0200 |
| commit | 6c00704a5ef09be46b1f05e2be477e493f37dd38 (patch) | |
| tree | a64fb142c62fd5cd49a9928b5125ea4e133f4471 /frontends/verilog | |
| parent | 022f570563d8b067e9638bc91bbd168f4c5cb817 (diff) | |
Another block of spelling fixes
Smaller this time
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/const2ast.cc | 2 | ||||
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index d54f1428..ebecb92f 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -136,7 +136,7 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le } } -// convert the verilog code for a constant to an AST node +// convert the Verilog code for a constant to an AST node AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn_z) { if (warn_z) { diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index bd7837b3..a7259358 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -281,7 +281,7 @@ supply1 { return TOK_SUPPLY1; } static bool printed_warning = false; if (!printed_warning) { log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n" - "Yosys does support them but it is recommended to use verilog `full_case' attributes instead!\n"); + "Yosys does support them but it is recommended to use Verilog `full_case' attributes instead!\n"); printed_warning = true; } return TOK_SYNOPSYS_FULL_CASE; @@ -290,7 +290,7 @@ supply1 { return TOK_SUPPLY1; } static bool printed_warning = false; if (!printed_warning) { log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n" - "Yosys does support them but it is recommended to use verilog `parallel_case' attributes instead!\n"); + "Yosys does support them but it is recommended to use Verilog `parallel_case' attributes instead!\n"); printed_warning = true; } return TOK_SYNOPSYS_PARALLEL_CASE; |