Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

16 files changed, 108 insertions, 47 deletions

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 5b3214f5..d548a679 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -34,6 +34,8 @@
 #include <stdarg.h>
 #include <math.h>
 
+YOSYS_NAMESPACE_BEGIN
+
 using namespace AST;
 using namespace AST_INTERNAL;
 
@@ -806,7 +808,7 @@ RTLIL::Const AstNode::realAsConst(int width)
 {
 	double v = round(realvalue);
 	RTLIL::Const result;
-	if (!isfinite(v)) {
+	if (!std::isfinite(v)) {
 		result.bits = std::vector<RTLIL::State>(width, RTLIL::State::Sx);
 	} else {
 		bool is_negative = v < 0;
@@ -1087,3 +1089,5 @@ void AST::use_internal_line_num()
 	get_line_num = &internal_get_line_num;
 }
 
+YOSYS_NAMESPACE_END
+
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 6c15c03a..83798edf 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -33,6 +33,8 @@
 #include <stdint.h>
 #include <set>
 
+YOSYS_NAMESPACE_BEGIN
+
 namespace AST
 {
 	// all node types, type2str() must be extended
@@ -285,4 +287,6 @@ namespace AST_INTERNAL
 	struct ProcessGenerator;
 }
 
+YOSYS_NAMESPACE_END
+
 #endif
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index b7f33635..0cc4f4c4 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -34,6 +34,8 @@
 #include <stdarg.h>
 #include <algorithm>
 
+YOSYS_NAMESPACE_BEGIN
+
 using namespace AST;
 using namespace AST_INTERNAL;
 
@@ -41,7 +43,7 @@ using namespace AST_INTERNAL;
 static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
 {
 	std::stringstream sstr;
-	sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
+	sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
 
 	RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
 	cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
@@ -75,7 +77,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
 	}
 
 	std::stringstream sstr;
-	sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
+	sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
 
 	RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype);
 	cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
@@ -104,7 +106,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
 static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 {
 	std::stringstream sstr;
-	sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
+	sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
 
 	RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
 	cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
@@ -139,7 +141,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
 	log_assert(cond.size() == 1);
 
 	std::stringstream sstr;
-	sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
+	sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
 
 	RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
 	cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
@@ -201,7 +203,7 @@ struct AST_INTERNAL::ProcessGenerator
 		// generate process and simple root case
 		proc = new RTLIL::Process;
 		proc->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
-		proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, RTLIL::autoidx++);
+		proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++);
 		for (auto &attr : always->attributes) {
 			if (attr.second->type != AST_CONSTANT)
 				log_error("Attribute `%s' with non-constant value at %s:%d!\n",
@@ -294,7 +296,7 @@ struct AST_INTERNAL::ProcessGenerator
 				wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
 						chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
 				if (chunk.wire->name.find('$') != std::string::npos)
-					wire_name += stringf("$%d", RTLIL::autoidx++);
+					wire_name += stringf("$%d", autoidx++);
 			} while (current_module->wires_.count(wire_name) > 0);
 
 			RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
@@ -1189,7 +1191,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_MEMRD:
 		{
 			std::stringstream sstr;
-			sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
+			sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
 
 			RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
 			cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@@ -1220,7 +1222,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_MEMWR:
 		{
 			std::stringstream sstr;
-			sstr << "$memwr$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
+			sstr << "$memwr$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
 
 			RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memwr");
 			cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@@ -1241,7 +1243,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
 			cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
 
-			cell->parameters["\\PRIORITY"] = RTLIL::Const(RTLIL::autoidx-1);
+			cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1);
 		}
 		break;
 
@@ -1257,7 +1259,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			log_assert(en.size() == 1);
 
 			std::stringstream sstr;
-			sstr << "$assert$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
+			sstr << "$assert$" << filename << ":" << linenum << "$" << (autoidx++);
 
 			RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$assert");
 			cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@@ -1399,3 +1401,5 @@ RTLIL::SigSpec AstNode::genWidthRTLIL(int width, RTLIL::SigSpec *subst_from,  RT
 	return sig;
 }
 
+YOSYS_NAMESPACE_END
+
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 5665cd43..c51692f1 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -34,6 +34,8 @@
 #include <stdarg.h>
 #include <math.h>
 
+YOSYS_NAMESPACE_BEGIN
+
 using namespace AST;
 using namespace AST_INTERNAL;
 
@@ -624,7 +626,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		id2ast->meminfo(mem_width, mem_size, addr_bits);
 
 		std::stringstream sstr;
-		sstr << "$mem2bits$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
+		sstr << "$mem2bits$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++);
 		std::string wire_id = sstr.str();
 
 		AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
@@ -744,7 +746,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 				buf = new AstNode(AST_GENBLOCK, body_ast->clone());
 			if (buf->str.empty()) {
 				std::stringstream sstr;
-				sstr << "$genblock$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
+				sstr << "$genblock$" << filename << ":" << linenum << "$" << (autoidx++);
 				buf->str = sstr.str();
 			}
 			std::map<std::string, std::string> name_map;
@@ -1091,7 +1093,7 @@ skip_dynamic_range_lvalue_expansion:;
 	if (stage > 1 && type == AST_ASSERT && current_block != NULL)
 	{
 		std::stringstream sstr;
-		sstr << "$assert$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
+		sstr << "$assert$" << filename << ":" << linenum << "$" << (autoidx++);
 		std::string id_check = sstr.str() + "_CHECK", id_en = sstr.str() + "_EN";
 
 		AstNode *wire_check = new AstNode(AST_WIRE);
@@ -1166,7 +1168,7 @@ skip_dynamic_range_lvalue_expansion:;
 			(children[0]->children.size() == 1 || children[0]->children.size() == 2))
 	{
 		std::stringstream sstr;
-		sstr << "$memwr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
+		sstr << "$memwr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++);
 		std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN";
 
 		if (type == AST_ASSIGN_EQ)
@@ -1364,27 +1366,27 @@ skip_dynamic_range_lvalue_expansion:;
 				}
 
 				newNode = new AstNode(AST_REALVALUE);
-				if (str == "\\$ln")         newNode->realvalue = log(x);
-				else if (str == "\\$log10") newNode->realvalue = log10(x);
-				else if (str == "\\$exp")   newNode->realvalue = exp(x);
-				else if (str == "\\$sqrt")  newNode->realvalue = sqrt(x);
-				else if (str == "\\$pow")   newNode->realvalue = pow(x, y);
-				else if (str == "\\$floor") newNode->realvalue = floor(x);
-				else if (str == "\\$ceil")  newNode->realvalue = ceil(x);
-				else if (str == "\\$sin")   newNode->realvalue = sin(x);
-				else if (str == "\\$cos")   newNode->realvalue = cos(x);
-				else if (str == "\\$tan")   newNode->realvalue = tan(x);
-				else if (str == "\\$asin")  newNode->realvalue = asin(x);
-				else if (str == "\\$acos")  newNode->realvalue = acos(x);
-				else if (str == "\\$atan")  newNode->realvalue = atan(x);
-				else if (str == "\\$atan2") newNode->realvalue = atan2(x, y);
-				else if (str == "\\$hypot") newNode->realvalue = hypot(x, y);
-				else if (str == "\\$sinh")  newNode->realvalue = sinh(x);
-				else if (str == "\\$cosh")  newNode->realvalue = cosh(x);
-				else if (str == "\\$tanh")  newNode->realvalue = tanh(x);
-				else if (str == "\\$asinh") newNode->realvalue = asinh(x);
-				else if (str == "\\$acosh") newNode->realvalue = acosh(x);
-				else if (str == "\\$atanh") newNode->realvalue = atanh(x);
+				if (str == "\\$ln")         newNode->realvalue = ::log(x);
+				else if (str == "\\$log10") newNode->realvalue = ::log10(x);
+				else if (str == "\\$exp")   newNode->realvalue = ::exp(x);
+				else if (str == "\\$sqrt")  newNode->realvalue = ::sqrt(x);
+				else if (str == "\\$pow")   newNode->realvalue = ::pow(x, y);
+				else if (str == "\\$floor") newNode->realvalue = ::floor(x);
+				else if (str == "\\$ceil")  newNode->realvalue = ::ceil(x);
+				else if (str == "\\$sin")   newNode->realvalue = ::sin(x);
+				else if (str == "\\$cos")   newNode->realvalue = ::cos(x);
+				else if (str == "\\$tan")   newNode->realvalue = ::tan(x);
+				else if (str == "\\$asin")  newNode->realvalue = ::asin(x);
+				else if (str == "\\$acos")  newNode->realvalue = ::acos(x);
+				else if (str == "\\$atan")  newNode->realvalue = ::atan(x);
+				else if (str == "\\$atan2") newNode->realvalue = ::atan2(x, y);
+				else if (str == "\\$hypot") newNode->realvalue = ::hypot(x, y);
+				else if (str == "\\$sinh")  newNode->realvalue = ::sinh(x);
+				else if (str == "\\$cosh")  newNode->realvalue = ::cosh(x);
+				else if (str == "\\$tanh")  newNode->realvalue = ::tanh(x);
+				else if (str == "\\$asinh") newNode->realvalue = ::asinh(x);
+				else if (str == "\\$acosh") newNode->realvalue = ::acosh(x);
+				else if (str == "\\$atanh") newNode->realvalue = ::atanh(x);
 				else log_abort();
 				goto apply_newNode;
 			}
@@ -1423,7 +1425,7 @@ skip_dynamic_range_lvalue_expansion:;
 
 		AstNode *decl = current_scope[str];
 		std::stringstream sstr;
-		sstr << "$func$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++) << "$";
+		sstr << "$func$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++) << "$";
 		std::string prefix = sstr.str();
 
 		size_t arg_count = 0;
@@ -1988,7 +1990,7 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
 			mem2reg_set.count(children[0]->id2ast) > 0 && children[0]->children[0]->children[0]->type != AST_CONSTANT)
 	{
 		std::stringstream sstr;
-		sstr << "$mem2reg_wr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
+		sstr << "$mem2reg_wr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++);
 		std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
 
 		int mem_width, mem_size, addr_bits;
@@ -2059,7 +2061,7 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
 		else
 		{
 			std::stringstream sstr;
-			sstr << "$mem2reg_rd$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
+			sstr << "$mem2reg_rd$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++);
 			std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
 
 			int mem_width, mem_size, addr_bits;
@@ -2421,3 +2423,5 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 	return AstNode::mkconst_bits(variables.at(str).val.bits, variables.at(str).is_signed);
 }
 
+YOSYS_NAMESPACE_END
+
diff --git a/frontends/ilang/ilang_frontend.cc b/frontends/ilang/ilang_frontend.cc
index 572a3572..2d4b99c5 100644
--- a/frontends/ilang/ilang_frontend.cc
+++ b/frontends/ilang/ilang_frontend.cc
@@ -26,6 +26,8 @@
 #include "kernel/register.h"
 #include "kernel/log.h"
 
+YOSYS_NAMESPACE_BEGIN
+
 void rtlil_frontend_ilang_yyerror(char const *s)
 {
 	log_error("Parser error in line %d: %s\n", rtlil_frontend_ilang_yyget_lineno(), s);
@@ -57,3 +59,5 @@ struct IlangFrontend : public Frontend {
 	}
 } IlangFrontend;
 
+YOSYS_NAMESPACE_END
+
diff --git a/frontends/ilang/ilang_frontend.h b/frontends/ilang/ilang_frontend.h
index 5e768c3b..317ec0d5 100644
--- a/frontends/ilang/ilang_frontend.h
+++ b/frontends/ilang/ilang_frontend.h
@@ -25,14 +25,18 @@
 #ifndef ILANG_FRONTEND_H
 #define ILANG_FRONTEND_H
 
-#include "kernel/rtlil.h"
+#include "kernel/yosys.h"
 #include <stdio.h>
 
+YOSYS_NAMESPACE_BEGIN
+
 namespace ILANG_FRONTEND {
 	void ilang_frontend(FILE *f, RTLIL::Design *design);
 	extern RTLIL::Design *current_design;
 }
 
+YOSYS_NAMESPACE_END
+
 extern int rtlil_frontend_ilang_yydebug;
 int rtlil_frontend_ilang_yylex(void);
 void rtlil_frontend_ilang_yyerror(char const *s);
diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y
index 38d3054b..ab763b2b 100644
--- a/frontends/ilang/parser.y
+++ b/frontends/ilang/parser.y
@@ -25,6 +25,7 @@
 %{
 #include <list>
 #include "ilang_frontend.h"
+YOSYS_NAMESPACE_BEGIN
 namespace ILANG_FRONTEND {
 	RTLIL::Design *current_design;
 	RTLIL::Module *current_module;
@@ -37,6 +38,8 @@ namespace ILANG_FRONTEND {
 	std::map<RTLIL::IdString, RTLIL::Const> attrbuf;
 }
 using namespace ILANG_FRONTEND;
+YOSYS_NAMESPACE_END
+USING_YOSYS_NAMESPACE
 %}
 
 %name-prefix "rtlil_frontend_ilang_yy"
@@ -44,8 +47,8 @@ using namespace ILANG_FRONTEND;
 %union {
 	char *string;
 	int integer;
-	RTLIL::Const *data;
-	RTLIL::SigSpec *sigspec;
+	YOSYS_NAMESPACE_PREFIX RTLIL::Const *data;
+	YOSYS_NAMESPACE_PREFIX RTLIL::SigSpec *sigspec;
 }
 
 %token <string> TOK_ID TOK_VALUE TOK_STRING
@@ -116,7 +119,7 @@ attr_stmt:
 
 autoidx_stmt:
 	TOK_AUTOIDX TOK_INT EOL {
-		RTLIL::autoidx = std::max(RTLIL::autoidx, $2);
+		autoidx = std::max(autoidx, $2);
 	};
 
 wire_stmt:
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index d5f172f0..da16ab33 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -21,6 +21,7 @@
 #include "kernel/register.h"
 #include "kernel/log.h"
 
+YOSYS_NAMESPACE_BEGIN
 using namespace PASS_DFFLIBMAP;
 
 struct token_t {
@@ -573,3 +574,5 @@ skip_cell:;
 	}
 } LibertyFrontend;
 
+YOSYS_NAMESPACE_END
+
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 80170394..6e692c5a 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -17,7 +17,7 @@
  *
  */
 
-#include "kernel/register.h"
+#include "kernel/yosys.h"
 #include "kernel/sigtools.h"
 #include "kernel/log.h"
 #include <unistd.h>
@@ -26,6 +26,8 @@
 #include <string.h>
 #include <dirent.h>
 
+USING_YOSYS_NAMESPACE
+
 #ifdef YOSYS_ENABLE_VERIFIC
 
 #pragma clang diagnostic push
@@ -768,6 +770,8 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 
 #endif /* YOSYS_ENABLE_VERIFIC */
 
+YOSYS_NAMESPACE_BEGIN
+
 struct VerificPass : public Pass {
 	VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
 	virtual void help()
@@ -945,3 +949,5 @@ struct VerificPass : public Pass {
 #endif
 } VerificPass;
  
+YOSYS_NAMESPACE_END
+
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index 446f5e50..a81e3010 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -39,6 +39,8 @@
 #include <string.h>
 #include <math.h>
 
+YOSYS_NAMESPACE_BEGIN
+
 using namespace AST;
 
 // divide an arbitrary length decimal number by two and return the rest
@@ -210,3 +212,5 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
 	return NULL;
 }
 
+YOSYS_NAMESPACE_END
+
diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l
index 00deeb0b..fdb9bb02 100644
--- a/frontends/verilog/lexer.l
+++ b/frontends/verilog/lexer.l
@@ -44,13 +44,16 @@
 #include "frontends/ast/ast.h"
 #include "parser.tab.h"
 
+USING_YOSYS_NAMESPACE
 using namespace AST;
 using namespace VERILOG_FRONTEND;
 
+YOSYS_NAMESPACE_BEGIN
 namespace VERILOG_FRONTEND {
 	std::vector<std::string> fn_stack;
 	std::vector<int> ln_stack;
 }
+YOSYS_NAMESPACE_END
 
 #define SV_KEYWORD(_tok) \
 	if (sv_mode) return _tok; \
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index ce7b9927..c62e761e 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -39,9 +39,11 @@
 #include "verilog_frontend.h"
 #include "kernel/log.h"
 
+USING_YOSYS_NAMESPACE
 using namespace AST;
 using namespace VERILOG_FRONTEND;
 
+YOSYS_NAMESPACE_BEGIN
 namespace VERILOG_FRONTEND {
 	int port_counter;
 	std::map<std::string, int> port_stubs;
@@ -56,6 +58,7 @@ namespace VERILOG_FRONTEND {
 	bool default_nettype_wire;
 	bool sv_mode;
 }
+YOSYS_NAMESPACE_END
 
 static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
 {
@@ -89,8 +92,8 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 
 %union {
 	std::string *string;
-	struct AstNode *ast;
-	std::map<std::string, AstNode*> *al;
+	struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
+	std::map<std::string, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
 	bool boolean;
 }
 
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 2cfa8ca7..8efd4d7c 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -38,6 +38,8 @@
 #include <stdio.h>
 #include <string.h>
 
+YOSYS_NAMESPACE_BEGIN
+
 static std::list<std::string> output_code;
 static std::list<std::string> input_buffer;
 static size_t input_buffer_charp;
@@ -427,3 +429,5 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m
 	return output;
 }
 
+YOSYS_NAMESPACE_END
+
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index cbc594e8..4466e1cb 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -34,6 +34,7 @@
 #include <sstream>
 #include <stdarg.h>
 
+YOSYS_NAMESPACE_BEGIN
 using namespace VERILOG_FRONTEND;
 
 // use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL
@@ -376,3 +377,5 @@ struct VerilogDefaults : public Pass {
 	}
 } VerilogDefaults;
 
+YOSYS_NAMESPACE_END
+
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h
index 6d01a153..dac5b3d0 100644
--- a/frontends/verilog/verilog_frontend.h
+++ b/frontends/verilog/verilog_frontend.h
@@ -29,12 +29,14 @@
 #ifndef VERILOG_FRONTEND_H
 #define VERILOG_FRONTEND_H
 
-#include "kernel/rtlil.h"
+#include "kernel/yosys.h"
 #include "frontends/ast/ast.h"
 #include <stdio.h>
 #include <stdint.h>
 #include <list>
 
+YOSYS_NAMESPACE_BEGIN
+
 namespace VERILOG_FRONTEND
 {
 	// this variable is set to a new AST_DESIGN node and then filled with the AST by the bison parser
@@ -53,6 +55,8 @@ namespace VERILOG_FRONTEND
 // the pre-processor
 std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::map<std::string, std::string> pre_defines_map, const std::list<std::string> include_dirs);
 
+YOSYS_NAMESPACE_END
+
 // the usual bison/flex stuff
 extern int frontend_verilog_yydebug;
 int frontend_verilog_yylex(void);
diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc
index 63dc85ac..f0545700 100644
--- a/frontends/vhdl2verilog/vhdl2verilog.cc
+++ b/frontends/vhdl2verilog/vhdl2verilog.cc
@@ -28,6 +28,8 @@
 #include <errno.h>
 #include <limits.h>
 
+YOSYS_NAMESPACE_BEGIN
+
 struct Vhdl2verilogPass : public Pass {
 	Vhdl2verilogPass() : Pass("vhdl2verilog", "importing VHDL designs using vhdl2verilog") { }
 	virtual void help()
@@ -190,3 +192,5 @@ struct Vhdl2verilogPass : public Pass {
 	}
 } Vhdl2verilogPass;
  
+YOSYS_NAMESPACE_END
+