diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-29 14:42:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-29 16:35:13 +0200 |
| commit | 397b00252dc0c4af725614bd12fc299147ba8efa (patch) | |
| tree | e7a1dfdd61f165a517036c4efdde2c53ef9076e7 /frontends | |
| parent | 48822e79a34880c5f0b07e9889e463e7b6d7111b (diff) | |
Added $shift and $shiftx cell types (needed for correct part select behavior)
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index cb666679..b7f33635 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -917,11 +917,17 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) children[0]->children[1]->clone() : children[0]->children[0]->clone()); fake_ast->children[0]->delete_children(); RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL(); - if (id2ast->range_right != 0) - shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right); - if (id2ast->range_swapped) - shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val); - RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shr", width, fake_ast->children[0]->genRTLIL(), shift_val); + if (id2ast->range_right != 0) { + shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right, fake_ast->children[1]->is_signed); + fake_ast->children[1]->is_signed = true; + } + if (id2ast->range_swapped) { + shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast->children[1]->is_signed); + fake_ast->children[1]->is_signed = true; + } + if (SIZE(shift_val) >= 32) + fake_ast->children[1]->is_signed = true; + RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val); delete left_at_zero_ast; delete right_at_zero_ast; delete fake_ast; |