diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-11-07 19:19:53 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-07 19:20:20 +0100 |
| commit | d7cb62ac96c34a13707112718fe06353a4f34526 (patch) | |
| tree | a431684a231b7f2bc874f0d3d6ff925a32f29595 /frontends | |
| parent | 02f4f89fdba402a1fa74f2f88291f7e1a37db0f2 (diff) | |
Fixed more extend vs. extend_u0 issues
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 4 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index c701c2fa..0c9c9be7 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -961,7 +961,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) return sig; } - // just pass thru the signal. the parent will evaluate the is_signed property and inperpret the SigSpec accordingly + // just pass thru the signal. the parent will evaluate the is_signed property and interpret the SigSpec accordingly case AST_TO_SIGNED: case AST_TO_UNSIGNED: { RTLIL::SigSpec sig = children[0]->genRTLIL(); @@ -1346,7 +1346,7 @@ RTLIL::SigSpec AstNode::genWidthRTLIL(int width, RTLIL::SigSpec *subst_from, RT genRTLIL_subst_to = backup_subst_to; if (width >= 0) - widthExtend(this, sig, width, is_signed); + sig.extend_u0(width, is_signed); return sig; } diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 7b5ae064..449ade43 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -441,7 +441,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width = children[1]->range_left - children[1]->range_right + 1; if (width != int(children[0]->bits.size())) { RTLIL::SigSpec sig(children[0]->bits); - sig.extend(width, children[0]->is_signed); + sig.extend_u0(width, children[0]->is_signed); delete children[0]; children[0] = mkconst_bits(sig.as_const().bits, children[0]->is_signed); } |