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authorClifford Wolf <clifford@clifford.at>2013-03-03 10:36:23 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-03 10:36:23 +0100
commit65e5e1658cd18c75bed2097d99acc66216e8856d (patch)
tree6f24aa1ec6d59b51e54d1e00280171f443311f8b /kernel/celltypes.h
parent4fcb9a7b9907cd0242ce6f9c4a3855ba20ca9017 (diff)
Added library support to celltypes class and show pass
Diffstat (limited to 'kernel/celltypes.h')
-rw-r--r--kernel/celltypes.h39
1 files changed, 35 insertions, 4 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index a13cbf32..1e56a4dd 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -27,6 +27,7 @@
struct CellTypes
{
std::set<std::string> cell_types;
+ std::vector<const RTLIL::Design*> designs;
void setup_internals()
{
@@ -99,20 +100,39 @@ struct CellTypes
cell_types.insert("$_DFF_PP1_");
}
+ void setup_design(const RTLIL::Design *design)
+ {
+ designs.push_back(design);
+ }
+
void clear()
{
cell_types.clear();
+ designs.clear();
}
bool cell_known(std::string type)
{
- return cell_types.count(type) > 0;
+ if (cell_types.count(type) > 0)
+ return true;
+ for (auto design : designs)
+ if (design->modules.count(type) > 0)
+ return true;
+ return false;
}
bool cell_output(std::string type, std::string port)
{
- if (!cell_known(type))
+ if (cell_types.count(type) == 0) {
+ for (auto design : designs)
+ if (design->modules.count(type) > 0) {
+ if (design->modules.at(type)->wires.count(port))
+ return design->modules.at(type)->wires.at(port)->port_output;
+ return false;
+ }
return false;
+ }
+
if (port == "\\Y" || port == "\\Q" || port == "\\RD_DATA")
return true;
if (type == "$memrd" && port == "\\DATA")
@@ -124,9 +144,20 @@ struct CellTypes
bool cell_input(std::string type, std::string port)
{
- if (!cell_known(type))
+ if (cell_types.count(type) == 0) {
+ for (auto design : designs)
+ if (design->modules.count(type) > 0) {
+ if (design->modules.at(type)->wires.count(port))
+ return design->modules.at(type)->wires.at(port)->port_input;
+ return false;
+ }
return false;
- return !cell_output(type, port);
+ }
+
+ if (cell_types.count(type) > 0)
+ return !cell_output(type, port);
+
+ return false;
}
static RTLIL::Const eval(std::string type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)