diff options
author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:29:11 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:29:11 +0100 |
commit | f71e27dbf15d063ca45378ff2eb2d8102220f199 (patch) | |
tree | 67137e2ddf4dcf588fa4397d15d3e7648805a896 /kernel/rtlil.cc | |
parent | 609caa23b5e12547c043dc4a1827d1a531af1992 (diff) |
Remove auto_wire framework (smarter than the verilog standard)
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r-- | kernel/rtlil.cc | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index afd7ca2f..5bfb33a2 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -265,11 +265,6 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name)); } -void RTLIL::Module::update_auto_wires(std::map<RTLIL::IdString, int>) -{ - log_error("Module `%s' has automatic wires bu no HDL backend to handle it!\n", id2cstr(name)); -} - size_t RTLIL::Module::count_id(RTLIL::IdString id) { return wires.count(id) + memories.count(id) + cells.count(id) + processes.count(id); @@ -779,7 +774,6 @@ RTLIL::Wire::Wire() port_id = 0; port_input = false; port_output = false; - auto_width = false; } RTLIL::Memory::Memory() |