Use only module->addCell() and module->remove() to create and delete cells

2 files changed, 54 insertions, 4 deletions

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 83524d79..17e4a273 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -782,8 +782,14 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
 	for (auto &it : memories)
 		new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
 
-	for (auto &it : cells)
-		new_mod->cells[it.first] = new RTLIL::Cell(*it.second);
+	for (auto &it : cells) {
+		new_mod->cells[it.first] = new RTLIL::Cell;
+		new_mod->cells[it.first]->name = it.second->name;
+		new_mod->cells[it.first]->type = it.second->type;
+		new_mod->cells[it.first]->connections = it.second->connections;
+		new_mod->cells[it.first]->parameters = it.second->parameters;
+		new_mod->cells[it.first]->attributes = it.second->attributes;
+	}
 
 	for (auto &it : processes)
 		new_mod->processes[it.first] = it.second->clone();
@@ -834,6 +840,33 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
 	delete cell;
 }
 
+void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
+{
+	assert(wires[wire->name] == wire);
+	wires.erase(wire->name);
+	wire->name = new_name;
+	add(wire);
+}
+
+void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
+{
+	assert(cells[cell->name] == cell);
+	cells.erase(cell->name);
+	cell->name = new_name;
+	add(cell);
+}
+
+void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
+{
+	assert(count_id(old_name) != 0);
+	if (wires.count(old_name))
+		rename(wires.at(old_name), new_name);
+	else if (cells.count(old_name))
+		rename(cells.at(old_name), new_name);
+	else
+		log_abort();
+}
+
 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
 {
 	if (a->port_id && !b->port_id)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 59db099f..e1e4a54b 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -271,7 +271,8 @@ struct RTLIL::Design {
 		return attributes.at(id).as_bool();            \
 	}
 
-struct RTLIL::Module {
+struct RTLIL::Module
+{
 	RTLIL::IdString name;
 	std::set<RTLIL::IdString> avail_parameters;
 	std::map<RTLIL::IdString, RTLIL::Wire*> wires;
@@ -295,6 +296,10 @@ struct RTLIL::Module {
 	void add(RTLIL::Cell *cell);
 	void remove(RTLIL::Cell *cell);
 
+	void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
+	void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);
+	void rename(RTLIL::IdString old_name, RTLIL::IdString new_name);
+
 	RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
 	RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
 
@@ -444,7 +449,19 @@ struct RTLIL::Memory {
 	Memory();
 };
 
-struct RTLIL::Cell {
+struct RTLIL::Cell
+{
+protected:
+	// Use module->addCell() and module->remove() to create or destroy modules.
+	friend struct RTLIL::Module;
+	Cell() { };
+	~Cell() { };
+
+public:
+	// do not copy simply cells
+	Cell(RTLIL::Cell &other) = delete;
+	void operator=(RTLIL::Cell &other) = delete;
+
 	RTLIL::IdString name;
 	RTLIL::IdString type;
 	std::map<RTLIL::IdString, RTLIL::SigSpec> connections;