summaryrefslogtreecommitdiff
path: root/kernel
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2015-01-24 00:13:27 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-24 00:13:27 +0100
commit43951099cf46b5a0a25bdebb001685a89dfe6c82 (patch)
treeb95a7ef79401216e1e65b30691b4ecaa2e7491af /kernel
parent1cb4c925d03de289f37a40b6eceb57ced8dce295 (diff)
Added dict/pool.sort()
Diffstat (limited to 'kernel')
-rw-r--r--kernel/hashlib.h14
-rw-r--r--kernel/rtlil.cc30
-rw-r--r--kernel/rtlil.h4
3 files changed, 48 insertions, 0 deletions
diff --git a/kernel/hashlib.h b/kernel/hashlib.h
index 52b38a06..8c977de2 100644
--- a/kernel/hashlib.h
+++ b/kernel/hashlib.h
@@ -457,6 +457,13 @@ public:
return entries[i].udata.second;
}
+ template<typename Compare = std::less<K>>
+ void sort(Compare comp = Compare())
+ {
+ std::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata.first, a.udata.first); });
+ do_rehash();
+ }
+
void swap(dict &other)
{
hashtable.swap(other.hashtable);
@@ -760,6 +767,13 @@ public:
return i >= 0;
}
+ template<typename Compare = std::less<K>>
+ void sort(Compare comp = Compare())
+ {
+ std::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata, a.udata); });
+ do_rehash();
+ }
+
void swap(pool &other)
{
hashtable.swap(other.hashtable);
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index aea99347..3fb98d1e 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -373,6 +373,14 @@ void RTLIL::Design::remove(RTLIL::Module *module)
delete module;
}
+void RTLIL::Design::sort()
+{
+ scratchpad.sort();
+ modules_.sort(sort_by_id_str());
+ for (auto &it : modules_)
+ it.second->sort();
+}
+
void RTLIL::Design::check()
{
#ifndef NDEBUG
@@ -976,6 +984,21 @@ namespace {
}
#endif
+void RTLIL::Module::sort()
+{
+ wires_.sort(sort_by_id_str());
+ cells_.sort(sort_by_id_str());
+ avail_parameters.sort(sort_by_id_str());
+ memories.sort(sort_by_id_str());
+ processes.sort(sort_by_id_str());
+ for (auto &it : cells_)
+ it.second->sort();
+ for (auto &it : wires_)
+ it.second->attributes.sort(sort_by_id_str());
+ for (auto &it : memories)
+ it.second->attributes.sort(sort_by_id_str());
+}
+
void RTLIL::Module::check()
{
#ifndef NDEBUG
@@ -1908,6 +1931,13 @@ const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
return parameters.at(paramname);
}
+void RTLIL::Cell::sort()
+{
+ connections_.sort(sort_by_id_str());
+ parameters.sort(sort_by_id_str());
+ attributes.sort(sort_by_id_str());
+}
+
void RTLIL::Cell::check()
{
#ifndef NDEBUG
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index dae684d9..d8ebae71 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -788,6 +788,7 @@ struct RTLIL::Design
bool scratchpad_get_bool(std::string varname, bool default_value = false) const;
std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const;
+ void sort();
void check();
void optimize();
@@ -863,6 +864,8 @@ public:
virtual ~Module();
virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters);
virtual size_t count_id(RTLIL::IdString id);
+
+ virtual void sort();
virtual void check();
virtual void optimize();
@@ -1136,6 +1139,7 @@ public:
void setParam(RTLIL::IdString paramname, RTLIL::Const value);
const RTLIL::Const &getParam(RTLIL::IdString paramname) const;
+ void sort();
void check();
void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);