diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-10-10 17:22:08 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-10-10 17:22:08 +0200 |
commit | bbd808072be859074a023795a15bebab87cbfba8 (patch) | |
tree | 970f9b71b8f858e62f273d1cdf2f2fdca85becdb /kernel | |
parent | 7cb0d3aa1acf37025e82846f809d066356a98843 (diff) |
Added format __attribute__ to stringf()
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/satgen.h | 2 | ||||
-rw-r--r-- | kernel/yosys.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/kernel/satgen.h b/kernel/satgen.h index 779c9750..d556f4f3 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -68,7 +68,7 @@ struct SatGen else vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE); } else { - std::string name = pf + stringf(bit.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(bit.wire->name), bit.offset); + std::string name = pf + (bit.wire->width == 1 ? stringf("%s", log_id(bit.wire)) : stringf("%s [%d]", log_id(bit.wire->name), bit.offset)); vec.push_back(ez->frozen_literal(name)); imported_signals[pf][bit] = vec.back(); } diff --git a/kernel/yosys.h b/kernel/yosys.h index c5da9f04..d3f88564 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -82,7 +82,7 @@ namespace RTLIL { struct Cell; } -std::string stringf(const char *fmt, ...); +std::string stringf(const char *fmt, ...) __attribute__ ((format (printf, 1, 2))); std::string vstringf(const char *fmt, va_list ap); template<typename T> int GetSize(const T &obj) { return obj.size(); } int GetSize(RTLIL::Wire *wire); |