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author | Clifford Wolf <clifford@clifford.at> | 2013-07-20 15:19:12 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-07-20 15:19:12 +0200 |
commit | 61ed6b32d1f5fbfda9c6effdaa678092f8156bfa (patch) | |
tree | 3a53692cbd93a09eabeb67eff5e9e4ace5cf1a3e /manual/FILES_StateOfTheArt/always03.v | |
parent | 3650fd7fbe45a00792770d9ecb9397bc27ea0845 (diff) |
Added Yosys Manual
Diffstat (limited to 'manual/FILES_StateOfTheArt/always03.v')
-rw-r--r-- | manual/FILES_StateOfTheArt/always03.v | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/manual/FILES_StateOfTheArt/always03.v b/manual/FILES_StateOfTheArt/always03.v new file mode 100644 index 00000000..53386acd --- /dev/null +++ b/manual/FILES_StateOfTheArt/always03.v @@ -0,0 +1,23 @@ +module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7, + out1, out2, out3); + +input clock, in1, in2, in3, in4, in5, in6, in7; +output out1, out2, out3; +reg out1, out2, out3; + +always @(posedge clock) begin + out1 = in1; + if (in2) + out1 = !out1; + out2 <= out1; + if (in3) + out2 <= out2; + if (in4) + if (in5) + out3 <= in6; + else + out3 <= in7; + out1 = out1 ^ out2; +end + +endmodule |