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authorClifford Wolf <clifford@clifford.at>2014-01-29 12:15:38 +0100
committerClifford Wolf <clifford@clifford.at>2014-01-29 12:15:38 +0100
commitcbe77bf84465ea0c4120e865189b07329b862468 (patch)
tree17728929b55a1ea72fb62b40b7d22a3989ab6de7 /manual/PRESENTATION_Intro/mycells.v
parentaceab5fc08ccba493b81cced8f24406ae76ac7bc (diff)
presentation progress
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+
+module NOT(A, Y);
+input A;
+output Y = ~A;
+endmodule
+
+module NAND(A, B, Y);
+input A, B;
+output Y = ~(A & B);
+endmodule
+
+module NOR(A, B, Y);
+input A, B;
+output Y = ~(A | B);
+endmodule
+
+module DFF(C, D, Q);
+input C, D;
+output reg Q;
+always @(posedge C)
+ Q <= D;
+endmodule
+