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authorClifford Wolf <clifford@clifford.at>2014-06-26 22:05:39 +0200
committerClifford Wolf <clifford@clifford.at>2014-06-26 22:05:39 +0200
commit3e96ce86809fa0a4ea737fa4a9d3e6261f40a191 (patch)
tree1cd6ff84af76575c3d1695b170e157090267fea7 /manual/PRESENTATION_Intro
parent076182c34e34b5e59eb5d89d5001f7547102bb4d (diff)
Progress in presentation
Diffstat (limited to 'manual/PRESENTATION_Intro')
-rw-r--r--manual/PRESENTATION_Intro/counter.ys11
1 files changed, 6 insertions, 5 deletions
diff --git a/manual/PRESENTATION_Intro/counter.ys b/manual/PRESENTATION_Intro/counter.ys
index bcfe387e..8b3390ed 100644
--- a/manual/PRESENTATION_Intro/counter.ys
+++ b/manual/PRESENTATION_Intro/counter.ys
@@ -2,17 +2,18 @@
read_verilog counter.v
hierarchy -check -top counter
-show -stretch -format pdf -prefix counter_00
+show -notitle -stretch -format pdf -prefix counter_00
# the high-level stuff
proc; opt; memory; opt; fsm; opt
-show -stretch -format pdf -prefix counter_01
+show -notitle -stretch -format pdf -prefix counter_01
# mapping to internal cell library
-techmap; splitnets -ports; opt
+techmap; opt
-show -stretch -format pdf -prefix counter_02
+splitnets -ports;;
+show -notitle -stretch -format pdf -prefix counter_02
# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
@@ -23,4 +24,4 @@ abc -liberty mycells.lib
# cleanup
clean
-show -stretch -lib mycells.v -format pdf -prefix counter_03
+show -notitle -stretch -lib mycells.v -format pdf -prefix counter_03