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| author | Clifford Wolf <clifford@clifford.at> | 2014-06-29 09:14:49 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-06-29 09:14:49 +0200 |
| commit | 3a3f5d5923840f44a6fb30fc7d70b6ed6ad7ccbb (patch) | |
| tree | 9631b0031c052155abb3634d172b9fe099308ac6 /manual/presentation.tex | |
| parent | 89c85cac419b7dc60e3776a250bcdc39dcb8980b (diff) | |
Progress in presentation
Diffstat (limited to 'manual/presentation.tex')
| -rw-r--r-- | manual/presentation.tex | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/manual/presentation.tex b/manual/presentation.tex index d098e815..a76a1c00 100644 --- a/manual/presentation.tex +++ b/manual/presentation.tex @@ -122,6 +122,25 @@ non-synthesis applications (such as formal equivialence checking) and writing extensions to Yosys using the C++ API. \end{frame} +\section{About me} +\begin{frame}{About me} +Hi! I'm Clifford Wolf. + +\bigskip +I like writing open source software. For example: +\begin{itemize} +\item Yosys +\item OpenSCAD (now maintained by Marius Kintel) +\item SPL (a not very popular scripting language) +\item EmbedVM (a very simple colipler+vm for 8 bit micros) +\item Lib(X)SVF (a library to play SVF/XSVF files over JTAG, used at LHC) +\item ROCK Linux (inactive since 2010) +\end{itemize} + +\bigskip +What do I do for a living? Ask me off the record.. +\end{frame} + \section{Outline} \begin{frame}{Outline} Yosys is an Open Source Verilog synthesis tool, and more. |