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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-20 15:19:12 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-20 15:19:12 +0200 |
| commit | 61ed6b32d1f5fbfda9c6effdaa678092f8156bfa (patch) | |
| tree | 3a53692cbd93a09eabeb67eff5e9e4ace5cf1a3e /manual/weblinks.bib | |
| parent | 3650fd7fbe45a00792770d9ecb9397bc27ea0845 (diff) | |
Added Yosys Manual
Diffstat (limited to 'manual/weblinks.bib')
| -rw-r--r-- | manual/weblinks.bib | 140 |
1 files changed, 140 insertions, 0 deletions
diff --git a/manual/weblinks.bib b/manual/weblinks.bib new file mode 100644 index 00000000..9b6032ed --- /dev/null +++ b/manual/weblinks.bib @@ -0,0 +1,140 @@ +
+@misc{YosysGit,
+ author = {Clifford Wolf},
+ title = {{Yosys Open SYnthesis Suite (YOSYS)}},
+ note = {\url{http://github.com/cliffordwolf/yosys}}
+}
+
+@misc{YosysTestsGit,
+ author = {Clifford Wolf},
+ title = {{Yosys Test Bench}},
+ note = {\url{http://github.com/cliffordwolf/yosys-tests}}
+}
+
+@misc{VlogHammer,
+ author = {Clifford Wolf},
+ title = {{VlogHammer Verilog Synthesis Regression Tests}},
+ note = {\url{http://github.com/cliffordwolf/VlogHammer}}
+}
+
+@misc{Icarus,
+ author = {Stephen Williams},
+ title = {{Icarus Verilog}},
+ note = {Version 0.8.7, \url{http://iverilog.icarus.com/}}
+}
+
+@misc{VTR,
+ author= {Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},
+ title = {{The Verilog-to-Routing (VTR) Project for FPGAs}},
+ note = {Version 1.0, \url{https://code.google.com/p/vtr-verilog-to-routing/}}
+}
+
+@misc{HANA,
+ author = {Parvez Ahmad},
+ title = {{HDL Analyzer and Netlist Architect (HANA)}},
+ note = {Verison linux64-1.0-alpha (2012-10-14), \url{http://sourceforge.net/projects/sim-sim/}}
+}
+
+@misc{MVSIS,
+ author = {MVSIS group at Berkeley studies logic synthesis and verification for VLSI design},
+ title = {{MVSIS: Logic Synthesis and Verification}},
+ note = {Version 3.0, \url{http://embedded.eecs.berkeley.edu/mvsis/}}
+}
+
+@misc{VIS,
+ author = {{The VIS group}},
+ title = {{VIS: A system for Verification and Synthesis}},
+ note = {Version 2.4, \url{http://vlsi.colorado.edu/~vis/}}
+}
+
+@misc{ABC,
+ author = {{Berkeley Logic Synthesis and Verification Group}},
+ title = {{ABC: A System for Sequential Synthesis and Verification}},
+ note = {HQ Rev b5750272659f, 2012-10-28, \url{http://www.eecs.berkeley.edu/~alanmi/abc/}}
+}
+
+@misc{AIGER,
+ author = {{Armin Biere, Johannes Kepler University Linz, Austria}},
+ title = {{AIGER}},
+ note = {\url{http://fmv.jku.at/aiger/}}
+}
+
+@misc{XilinxWebPACK,
+ author = {{Xilinx, Inc.}},
+ title = {{ISE WebPACK Design Software}},
+ note = {\url{http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm}}
+}
+
+@misc{QuartusWeb,
+ author = {{Altera, Inc.}},
+ title = {{Quartus II Web Edition Software}},
+ note = {\url{http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html}}
+}
+
+@misc{OR1200,
+ title = {{OpenRISC 1200 CPU}},
+ note = {\url{http://opencores.org/or1k/OR1200\_OpenRISC\_Processor}}
+}
+
+@misc{openMSP430,
+ title = {{openMSP430 CPU}},
+ note = {\url{http://opencores.org/project,openmsp430}}
+}
+
+@misc{i2cmaster,
+ title = {{OpenCores I$^2$C Core}},
+ note = {\url{http://opencores.org/project,i2c}}
+}
+
+@misc{k68,
+ title = {{OpenCores k68 Core}},
+ note = {\url{http://opencores.org/project,k68}}
+}
+
+@misc{bison,
+ title = {{GNU Bison}},
+ note = {\url{http://www.gnu.org/software/bison/}}
+}
+
+@misc{flex,
+ title = {{Flex}},
+ note = {\url{http://flex.sourceforge.net/}}
+}
+
+@misc{C_to_Verilog,
+ title = {{C-to-Verilog}},
+ note = {\url{http://www.c-to-verilog.com/}}
+}
+
+@misc{LegUp,
+ title = {{LegUp}},
+ note = {\url{http://legup.eecg.utoronto.ca/}}
+}
+
+@misc{LibertyFormat,
+ title = {{The Liberty Library Modeling Standard}},
+ note = {\url{http://www.opensourceliberty.org/}}
+}
+
+@misc{ASIC-WORLD,
+ title = {{World of ASIC}},
+ note = {\url{http://www.asic-world.com/}}
+}
+
+@misc{Formality,
+ title = {{Synopsys Formality Equivalence Checking}},
+ note = {\url{http://www.synopsys.com/Tools/Verification/FormalEquivalence/Pages/Formality.aspx}},
+}
+
+@misc{bigint,
+ author = {Matt McCutchen},
+ title = {{C++ Big Integer Library}},
+ note = {\url{http://mattmccutchen.net/bigint/}}
+}
+
+@misc{smallsha1,
+ author = {Micael Hildenborg},
+ title = {{smallsha1}},
+ note = {\url{https://code.google.com/p/smallsha1/}}
+}
+
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