diff options
| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-07-12 13:41:39 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-07-27 20:57:41 +0200 |
| commit | be67894e355103dfffb665e4fafa065d9744974e (patch) | |
| tree | 176e37b4b5cb766f86dd6220f9e963ab7e56745b /manual | |
| parent | 15bd0864355347f7faccae0d2a0bbddd037dd531 (diff) | |
Some spelling errors fixed
Gbp-Pq: Name 0009-Some-spelling-errors-fixed.patch
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 2 | ||||
| -rw-r--r-- | manual/command-reference-manual.tex | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 964875d5..ae5cf094 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -240,7 +240,7 @@ An RTLIL::Wire object has the following properties: As with modules, the attributes can be Verilog attributes imported by the Verilog frontend or attributes assigned by passes. -In Yosys, busses (signal vectors) are represented using a single wire object +In Yosys, buses (signal vectors) are represented using a single wire object with a width > 1. So Yosys does not convert signal vectors to individual signals. This makes some aspects of RTLIL more complex but enables Yosys to be used for coarse grain synthesis where the cells of the target architecture operate on diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index 8af8ccdd..3452ccb0 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -2859,7 +2859,7 @@ to a graphics file (usually SVG or PostScript). assigned to each unique value of this attribute. -width - annotate busses with a label indicating the width of the bus. + annotate buses with a label indicating the width of the bus. -signed mark ports (A, B) that are declared as signed (using the [AB]_SIGNED |