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authorClifford Wolf <clifford@clifford.at>2014-07-26 16:00:30 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 16:00:30 +0200
commita84cb0493566f8f5eb610c6d7b67dda85b0f227b (patch)
treee4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/cmds/select.cc
parentcd6574ecf652901573cbc6b89e1a59dd383ec496 (diff)
parentf8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (diff)
Merge automatic and manual code changes for new cell connections API
Diffstat (limited to 'passes/cmds/select.cc')
-rw-r--r--passes/cmds/select.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 5d991d03..e0f1a6d6 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -380,7 +380,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0)
selected_wires.insert(it.second);
- for (auto &conn : mod->connections_)
+ for (auto &conn : mod->connections())
{
std::vector<RTLIL::SigBit> conn_lhs = conn.first.to_sigbit_vector();
std::vector<RTLIL::SigBit> conn_rhs = conn.second.to_sigbit_vector();
@@ -396,7 +396,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
}
for (auto &cell : mod->cells)
- for (auto &conn : cell.second->connections_)
+ for (auto &conn : cell.second->connections())
{
char last_mode = '-';
for (auto &rule : rules) {