diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 19:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | a233762a815fc180b371f699e865a7d7aed77bca (patch) | |
| tree | 722e54921bbc09595c046c6045cd531445945fc9 /passes/cmds/setundef.cc | |
| parent | 3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff) | |
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'passes/cmds/setundef.cc')
| -rw-r--r-- | passes/cmds/setundef.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 9d59834c..3a99c0ce 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -48,7 +48,7 @@ struct SetundefWorker void operator()(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.chunks) + for (auto &c : sig.__chunks) if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1) c.data.bits.at(0) = next_bit(); sig.optimize(); @@ -141,7 +141,7 @@ struct SetundefPass : public Pass { undriven_signals.del(sigmap(conn.second)); RTLIL::SigSpec sig = undriven_signals.export_all(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) bits.append(next_bit()); |