summaryrefslogtreecommitdiff
path: root/passes/cmds/setundef.cc
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
commitcc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 (patch)
tree2d417ab32f95d109a0d8438ae7a14acf51783c5b /passes/cmds/setundef.cc
parent665759fceee4a0db3e776b7912e976eea2ff29a3 (diff)
Renamed RTLIL::{Module,Cell}::connections to connections_
Diffstat (limited to 'passes/cmds/setundef.cc')
-rw-r--r--passes/cmds/setundef.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 6c4bb16c..e1005a27 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -135,7 +135,7 @@ struct SetundefPass : public Pass {
CellTypes ct(design);
for (auto &it : module->cells)
- for (auto &conn : it.second->connections)
+ for (auto &conn : it.second->connections_)
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
undriven_signals.del(sigmap(conn.second));
@@ -144,7 +144,7 @@ struct SetundefPass : public Pass {
RTLIL::SigSpec bits;
for (int i = 0; i < c.width; i++)
bits.append(worker.next_bit());
- module->connections.push_back(RTLIL::SigSig(c, bits));
+ module->connections_.push_back(RTLIL::SigSig(c, bits));
}
}