Renamed port access function on RTLIL::Cell, added param access functions

3 files changed, 10 insertions, 10 deletions

diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index 62995a49..e3fde855 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -72,10 +72,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 			continue;
 		if (mod->get_bool_attribute("\\blackbox"))
 			continue;
-		if (it.second->has(name))
+		if (it.second->hasPort(name))
 			continue;
 
-		it.second->set(name, wire);
+		it.second->setPort(name, wire);
 		log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
 	}
 }
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index 3e13fd4d..30c80f73 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -176,7 +176,7 @@ struct ConnectPass : public Pass {
 			if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
 				log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
 
-			module->cells_.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig));
+			module->cells_.at(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig));
 		}
 		else
 			log_cmd_error("Expected -set, -unset, or -port.\n");
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 5fce2d6c..07c6150c 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -74,9 +74,9 @@ struct SpliceWorker
 			cell->parameters["\\OFFSET"] = offset;
 			cell->parameters["\\A_WIDTH"] = sig_a.size();
 			cell->parameters["\\Y_WIDTH"] = sig.size();
-			cell->set("\\A", sig_a);
-			cell->set("\\Y", module->addWire(NEW_ID, sig.size()));
-			new_sig = cell->get("\\Y");
+			cell->setPort("\\A", sig_a);
+			cell->setPort("\\Y", module->addWire(NEW_ID, sig.size()));
+			new_sig = cell->getPort("\\Y");
 		}
 
 		sliced_signals_cache[sig] = new_sig;
@@ -130,10 +130,10 @@ struct SpliceWorker
 			RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
 			cell->parameters["\\A_WIDTH"] = new_sig.size();
 			cell->parameters["\\B_WIDTH"] = sig2.size();
-			cell->set("\\A", new_sig);
-			cell->set("\\B", sig2);
-			cell->set("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size()));
-			new_sig = cell->get("\\Y");
+			cell->setPort("\\A", new_sig);
+			cell->setPort("\\B", sig2);
+			cell->setPort("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size()));
+			new_sig = cell->getPort("\\Y");
 		}
 
 		spliced_signals_cache[sig] = new_sig;