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| author | Clifford Wolf <clifford@clifford.at> | 2015-09-18 10:46:50 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-18 10:46:50 +0200 |
| commit | b7535a6c750108697161a72b5f2fe0001d0dd375 (patch) | |
| tree | 32f167507f583530f3943e9b6a158441be53ddbb /passes/fsm | |
| parent | c89ceee219b5a6412a64f585caeceb5db9528fe4 (diff) | |
Added $logic_not handling to fsm_detect
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index feeaa347..fd0ae44b 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -89,6 +89,8 @@ static bool check_state_users(RTLIL::SigSpec sig) RTLIL::Cell *cell = cellport.first; if (muxtree_cells.count(cell) > 0) continue; + if (cell->type == "$logic_not" && assign_map(cell->getPort("\\A")) == sig) + continue; if (cellport.second != "\\A" && cellport.second != "\\B") return false; if (!cell->hasPort("\\A") || !cell->hasPort("\\B") || !cell->hasPort("\\Y")) |