Added module->design and cell->module, wire->module pointers

2 files changed, 2 insertions, 2 deletions

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index a1361c68..67b57a94 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -117,7 +117,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 		RTLIL::Module *mod = new RTLIL::Module;
 		mod->name = celltype;
 		mod->attributes["\\blackbox"] = RTLIL::Const(1);
-		design->modules_[mod->name] = mod;
+		design->add(mod);
 
 		for (auto &decl : ports) {
 			RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname));
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 84c6b916..d0c9f4b5 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -105,7 +105,7 @@ struct SubmodWorker
 
 		RTLIL::Module *new_mod = new RTLIL::Module;
 		new_mod->name = submod.full_name;
-		design->modules_[new_mod->name] = new_mod;
+		design->add(new_mod);
 		int port_counter = 1, auto_name_counter = 1;
 
 		std::set<std::string> all_wire_names;