SigSpec refactoring: using the accessor functions everywhere

6 files changed, 89 insertions, 89 deletions

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 8a097916..68fb2e72 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -106,13 +106,13 @@ static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
 
 static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2, SigPool &regs, SigPool &conns, std::set<RTLIL::Wire*> &direct_wires)
 {
-	assert(s1.__width == 1);
-	assert(s2.__width == 1);
-	assert(s1.__chunks.size() == 1);
-	assert(s2.__chunks.size() == 1);
+	assert(s1.size() == 1);
+	assert(s2.size() == 1);
+	assert(s1.chunks().size() == 1);
+	assert(s2.chunks().size() == 1);
 
-	RTLIL::Wire *w1 = s1.__chunks[0].wire;
-	RTLIL::Wire *w2 = s2.__chunks[0].wire;
+	RTLIL::Wire *w1 = s1.chunks()[0].wire;
+	RTLIL::Wire *w2 = s2.chunks()[0].wire;
 
 	if (w1 == NULL || w2 == NULL)
 		return w2 == NULL;
@@ -235,14 +235,14 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 			} else {
 				s1.expand();
 				s2.expand();
-				assert(s1.__chunks.size() == s2.__chunks.size());
+				assert(s1.chunks().size() == s2.chunks().size());
 				RTLIL::SigSig new_conn;
-				for (size_t i = 0; i < s1.__chunks.size(); i++)
-					if (s1.__chunks[i] != s2.__chunks[i]) {
-						new_conn.first.append(s1.__chunks[i]);
-						new_conn.second.append(s2.__chunks[i]);
+				for (size_t i = 0; i < s1.chunks().size(); i++)
+					if (s1.chunks()[i] != s2.chunks()[i]) {
+						new_conn.first.append(s1.chunks()[i]);
+						new_conn.second.append(s2.chunks()[i]);
 					}
-				if (new_conn.first.__width > 0) {
+				if (new_conn.first.size() > 0) {
 					new_conn.first.optimize();
 					new_conn.second.optimize();
 					used_signals.add(new_conn.first);
@@ -258,8 +258,8 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 		if (!used_signals_nodrivers.check_any(sig)) {
 			std::string unused_bits;
 			sig.expand();
-			for (size_t i = 0; i < sig.__chunks.size(); i++) {
-				if (sig.__chunks[i].wire == NULL)
+			for (size_t i = 0; i < sig.chunks().size(); i++) {
+				if (sig.chunks()[i].wire == NULL)
 					continue;
 				if (!used_signals_nodrivers.check_any(sig)) {
 					if (!unused_bits.empty())
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index bee86771..1a1f0fe4 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -56,13 +56,13 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
 	all_signals.del(driven_signals);
 	RTLIL::SigSpec undriven_signals = all_signals.export_all();
 
-	for (auto &c : undriven_signals.__chunks)
+	for (auto &c : undriven_signals.chunks())
 	{
 		RTLIL::SigSpec sig = c;
 
 		if (c.wire->name[0] == '$')
 			sig = used_signals.extract(sig);
-		if (sig.__width == 0)
+		if (sig.size() == 0)
 			continue;
 
 		log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c));
@@ -74,7 +74,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
 static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
 {
 	RTLIL::SigSpec Y = cell->connections[out_port];
-	out_val.extend_u0(Y.__width, false);
+	out_val.extend_u0(Y.size(), false);
 
 	log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
 			cell->type.c_str(), cell->name.c_str(), info.c_str(),
@@ -99,11 +99,11 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
 	RTLIL::SigSpec sig_y = sigmap(cell->connections.at("\\Y"));
 
 	if (extend_u0) {
-		sig_a.extend_u0(sig_y.__width, a_signed);
-		sig_b.extend_u0(sig_y.__width, b_signed);
+		sig_a.extend_u0(sig_y.size(), a_signed);
+		sig_b.extend_u0(sig_y.size(), b_signed);
 	} else {
-		sig_a.extend(sig_y.__width, a_signed);
-		sig_b.extend(sig_y.__width, b_signed);
+		sig_a.extend(sig_y.size(), a_signed);
+		sig_b.extend(sig_y.size(), b_signed);
 	}
 
 	std::vector<RTLIL::SigBit> bits_a = sig_a, bits_b = sig_b, bits_y = sig_y;
@@ -153,7 +153,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
 		for (auto &it : grouped_bits[i]) {
 			for (auto &bit : it.second) {
 				new_conn.first.append_bit(bit);
-				new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.__width));
+				new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.size()));
 			}
 			new_a.append_bit(it.first.first);
 			new_b.append_bit(it.first.second);
@@ -162,12 +162,12 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
 		RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
 
 		c->connections["\\A"] = new_a;
-		c->parameters["\\A_WIDTH"] = new_a.__width;
+		c->parameters["\\A_WIDTH"] = new_a.size();
 		c->parameters["\\A_SIGNED"] = false;
 
 		if (b_name == "\\B") {
 			c->connections["\\B"] = new_b;
-			c->parameters["\\B_WIDTH"] = new_b.__width;
+			c->parameters["\\B_WIDTH"] = new_b.size();
 			c->parameters["\\B_SIGNED"] = false;
 		}
 
@@ -202,7 +202,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 	for (auto &cell_it : module->cells)
 		if (design->selected(module, cell_it.second)) {
 			if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") &&
-					cell_it.second->connections["\\A"].__width == 1 && cell_it.second->connections["\\Y"].__width == 1)
+					cell_it.second->connections["\\A"].size() == 1 && cell_it.second->connections["\\Y"].size() == 1)
 				invert_map[assign_map(cell_it.second->connections["\\Y"])] = assign_map(cell_it.second->connections["\\A"]);
 			cells.push_back(cell_it.second);
 		}
@@ -334,12 +334,12 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 						cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt")
 					replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx);
 				else
-					replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections.at("\\Y").__width));
+					replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections.at("\\Y").size()));
 				goto next_cell;
 			}
 		}
 
-		if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].__width == 1 &&
+		if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].size() == 1 &&
 				invert_map.count(assign_map(cell->connections["\\A"])) != 0) {
 			replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections["\\A"])));
 			goto next_cell;
@@ -460,35 +460,35 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			RTLIL::SigSpec new_a, new_b;
 			a.expand(), b.expand();
 
-			assert(a.__chunks.size() == b.__chunks.size());
-			for (size_t i = 0; i < a.__chunks.size(); i++) {
-				if (a.__chunks[i].wire == NULL && b.__chunks[i].wire == NULL && a.__chunks[i].data.bits[0] != b.__chunks[i].data.bits[0] &&
-						a.__chunks[i].data.bits[0] <= RTLIL::State::S1 && b.__chunks[i].data.bits[0] <= RTLIL::State::S1) {
+			assert(a.chunks().size() == b.chunks().size());
+			for (size_t i = 0; i < a.chunks().size(); i++) {
+				if (a.chunks()[i].wire == NULL && b.chunks()[i].wire == NULL && a.chunks()[i].data.bits[0] != b.chunks()[i].data.bits[0] &&
+						a.chunks()[i].data.bits[0] <= RTLIL::State::S1 && b.chunks()[i].data.bits[0] <= RTLIL::State::S1) {
 					RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ?  RTLIL::State::S0 : RTLIL::State::S1);
 					new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
 					replace_cell(module, cell, "empty", "\\Y", new_y);
 					goto next_cell;
 				}
-				if (a.__chunks[i] == b.__chunks[i])
+				if (a.chunks()[i] == b.chunks()[i])
 					continue;
-				new_a.append(a.__chunks[i]);
-				new_b.append(b.__chunks[i]);
+				new_a.append(a.chunks()[i]);
+				new_b.append(b.chunks()[i]);
 			}
 
-			if (new_a.__width == 0) {
+			if (new_a.size() == 0) {
 				RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ?  RTLIL::State::S1 : RTLIL::State::S0);
 				new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
 				replace_cell(module, cell, "empty", "\\Y", new_y);
 				goto next_cell;
 			}
 
-			if (new_a.__width < a.__width || new_b.__width < b.__width) {
+			if (new_a.size() < a.size() || new_b.size() < b.size()) {
 				new_a.optimize();
 				new_b.optimize();
 				cell->connections["\\A"] = new_a;
 				cell->connections["\\B"] = new_b;
-				cell->parameters["\\A_WIDTH"] = new_a.__width;
-				cell->parameters["\\B_WIDTH"] = new_b.__width;
+				cell->parameters["\\A_WIDTH"] = new_a.size();
+				cell->parameters["\\B_WIDTH"] = new_b.size();
 			}
 		}
 
@@ -550,10 +550,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				RTLIL::SigSpec a = assign_map(cell->connections["\\A"]);
 				RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
 
-				if (a.is_fully_const() && a.__width <= 32 && a.as_int() == 1)
+				if (a.is_fully_const() && a.size() <= 32 && a.as_int() == 1)
 					identity_wrt_b = true;
 
-				if (b.is_fully_const() && b.__width <= 32 && b.as_int() == 1)
+				if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1)
 					identity_wrt_a = true;
 			}
 
@@ -561,7 +561,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			{
 				RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
 
-				if (b.is_fully_const() && b.__width <= 32 && b.as_int() == 1)
+				if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1)
 					identity_wrt_a = true;
 			}
 
@@ -650,13 +650,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) {
 			RTLIL::SigSpec new_a, new_b, new_s;
-			int width = cell->connections.at("\\A").__width;
+			int width = cell->connections.at("\\A").size();
 			if ((cell->connections.at("\\A").is_fully_undef() && cell->connections.at("\\B").is_fully_undef()) ||
 					cell->connections.at("\\S").is_fully_undef()) {
 				replace_cell(module, cell, "mux undef", "\\Y", cell->connections.at("\\A"));
 				goto next_cell;
 			}
-			for (int i = 0; i < cell->connections.at("\\S").__width; i++) {
+			for (int i = 0; i < cell->connections.at("\\S").size(); i++) {
 				RTLIL::SigSpec old_b = cell->connections.at("\\B").extract(i*width, width);
 				RTLIL::SigSpec old_s = cell->connections.at("\\S").extract(i, 1);
 				if (old_b.is_fully_undef() || old_s.is_fully_undef())
@@ -665,12 +665,12 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				new_s.append(old_s);
 			}
 			new_a = cell->connections.at("\\A");
-			if (new_a.is_fully_undef() && new_s.__width > 0) {
-				new_a = new_b.extract((new_s.__width-1)*width, width);
-				new_b = new_b.extract(0, (new_s.__width-1)*width);
-				new_s = new_s.extract(0, new_s.__width-1);
+			if (new_a.is_fully_undef() && new_s.size() > 0) {
+				new_a = new_b.extract((new_s.size()-1)*width, width);
+				new_b = new_b.extract(0, (new_s.size()-1)*width);
+				new_s = new_s.extract(0, new_s.size()-1);
 			}
-			if (new_s.__width == 0) {
+			if (new_s.size() == 0) {
 				replace_cell(module, cell, "mux undef", "\\Y", new_a);
 				goto next_cell;
 			}
@@ -678,13 +678,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				replace_cell(module, cell, "mux undef", "\\Y", new_s);
 				goto next_cell;
 			}
-			if (cell->connections.at("\\S").__width != new_s.__width) {
+			if (cell->connections.at("\\S").size() != new_s.size()) {
 				cell->connections.at("\\A") = new_a;
 				cell->connections.at("\\B") = new_b;
 				cell->connections.at("\\S") = new_s;
-				if (new_s.__width > 1) {
+				if (new_s.size() > 1) {
 					cell->type = "$pmux";
-					cell->parameters["\\S_WIDTH"] = new_s.__width;
+					cell->parameters["\\S_WIDTH"] = new_s.size();
 				} else {
 					cell->type = "$mux";
 					cell->parameters.erase("\\S_WIDTH");
@@ -700,9 +700,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			assign_map.apply(a); \
 			if (a.is_fully_const()) { \
 				a.optimize(); \
-				if (a.__chunks.empty()) a.__chunks.push_back(RTLIL::SigChunk()); \
+				if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \
 				RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
-				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.__chunks[0].data, dummy_arg, \
+				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, dummy_arg, \
 						cell->parameters["\\A_SIGNED"].as_bool(), false, \
 						cell->parameters["\\Y_WIDTH"].as_int())); \
 				replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \
@@ -716,9 +716,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			assign_map.apply(a), assign_map.apply(b); \
 			if (a.is_fully_const() && b.is_fully_const()) { \
 				a.optimize(), b.optimize(); \
-				if (a.__chunks.empty()) a.__chunks.push_back(RTLIL::SigChunk()); \
-				if (b.__chunks.empty()) b.__chunks.push_back(RTLIL::SigChunk()); \
-				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.__chunks[0].data, b.__chunks[0].data, \
+				if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \
+				if (b.chunks().empty()) b.chunks().push_back(RTLIL::SigChunk()); \
+				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, b.chunks()[0].data, \
 						cell->parameters["\\A_SIGNED"].as_bool(), \
 						cell->parameters["\\B_SIGNED"].as_bool(), \
 						cell->parameters["\\Y_WIDTH"].as_int())); \
@@ -787,10 +787,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]);
 			RTLIL::SigSpec sig_y = assign_map(cell->connections["\\Y"]);
 
-			if (sig_b.is_fully_const() && sig_b.__width <= 32)
+			if (sig_b.is_fully_const() && sig_b.size() <= 32)
 				std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true;
 
-			if (sig_a.is_fully_def() && sig_a.__width <= 32)
+			if (sig_a.is_fully_def() && sig_a.size() <= 32)
 			{
 				int a_val = sig_a.as_int();
 
@@ -799,7 +799,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n",
 							cell->name.c_str(), module->name.c_str());
 
-					module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width)));
+					module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
 					module->remove(cell);
 
 					OPT_DID_SOMETHING = true;
@@ -807,7 +807,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					goto next_cell;
 				}
 
-				for (int i = 1; i < (a_signed ? sig_a.__width-1 : sig_a.__width); i++)
+				for (int i = 1; i < (a_signed ? sig_a.size()-1 : sig_a.size()); i++)
 					if (a_val == (1 << i))
 					{
 						log("Replacing multiply-by-%d cell `%s' in module `%s' with shift-by-%d.\n",
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index e844a420..61147f67 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -92,8 +92,8 @@ struct OptMuxtreeWorker
 				muxinfo_t muxinfo;
 				muxinfo.cell = cell;
 
-				for (int i = 0; i < sig_s.__width; i++) {
-					RTLIL::SigSpec sig = sig_b.extract(i*sig_a.__width, sig_a.__width);
+				for (int i = 0; i < sig_s.size(); i++) {
+					RTLIL::SigSpec sig = sig_b.extract(i*sig_a.size(), sig_a.size());
 					RTLIL::SigSpec ctrl_sig = assign_map(sig_s.extract(i, 1));
 					portinfo_t portinfo;
 					for (int idx : sig2bits(sig)) {
@@ -201,7 +201,7 @@ struct OptMuxtreeWorker
 
 			if (live_ports.size() == 1)
 			{
-				RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.__width, sig_a.__width);
+				RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size());
 				module->connections.push_back(RTLIL::SigSig(sig_y, sig_in));
 				module->cells.erase(mi.cell->name);
 				delete mi.cell;
@@ -211,7 +211,7 @@ struct OptMuxtreeWorker
 				RTLIL::SigSpec new_sig_a, new_sig_b, new_sig_s;
 
 				for (size_t i = 0; i < live_ports.size(); i++) {
-					RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.__width, sig_a.__width);
+					RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.size(), sig_a.size());
 					if (i == live_ports.size()-1) {
 						new_sig_a = sig_in;
 					} else {
@@ -223,11 +223,11 @@ struct OptMuxtreeWorker
 				mi.cell->connections["\\A"] = new_sig_a;
 				mi.cell->connections["\\B"] = new_sig_b;
 				mi.cell->connections["\\S"] = new_sig_s;
-				if (new_sig_s.__width == 1) {
+				if (new_sig_s.size() == 1) {
 					mi.cell->type = "$mux";
 					mi.cell->parameters.erase("\\S_WIDTH");
 				} else {
-					mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.__width);
+					mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size());
 				}
 			}
 		}
@@ -260,7 +260,7 @@ struct OptMuxtreeWorker
 		std::vector<int> results;
 		assign_map.apply(sig);
 		sig.expand();
-		for (auto &c : sig.__chunks)
+		for (auto &c : sig.chunks())
 			if (c.wire != NULL) {
 				bitDef_t bit(c.wire, c.offset);
 				if (bit2num.count(bit) == 0) {
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 4f1176d9..7ab7233c 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -48,7 +48,7 @@ struct OptReduceWorker
 		sig_a.expand();
 
 		RTLIL::SigSpec new_sig_a;
-		for (auto &chunk : sig_a.__chunks)
+		for (auto &chunk : sig_a.chunks())
 		{
 			if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S0) {
 				if (cell->type == "$reduce_and") {
@@ -85,7 +85,7 @@ struct OptReduceWorker
 		}
 		new_sig_a.sort_and_unify();
 
-		if (new_sig_a != sig_a || sig_a.__width != cell->connections["\\A"].__width) {
+		if (new_sig_a != sig_a || sig_a.size() != cell->connections["\\A"].size()) {
 			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
 			did_something = true;
 			OPT_DID_SOMETHING = true;
@@ -93,7 +93,7 @@ struct OptReduceWorker
 		}
 
 		cell->connections["\\A"] = new_sig_a;
-		cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.__width);
+		cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size());
 		return;
 	}
 
@@ -107,20 +107,20 @@ struct OptReduceWorker
 		std::set<RTLIL::SigSpec> handled_sig;
 
 		handled_sig.insert(sig_a);
-		for (int i = 0; i < sig_s.__width; i++)
+		for (int i = 0; i < sig_s.size(); i++)
 		{
-			RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.__width, sig_a.__width);
+			RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.size(), sig_a.size());
 			if (handled_sig.count(this_b) > 0)
 				continue;
 
 			RTLIL::SigSpec this_s = sig_s.extract(i, 1);
-			for (int j = i+1; j < sig_s.__width; j++) {
-				RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.__width, sig_a.__width);
+			for (int j = i+1; j < sig_s.size(); j++) {
+				RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.size(), sig_a.size());
 				if (this_b == that_b)
 					this_s.append(sig_s.extract(j, 1));
 			}
 
-			if (this_s.__width > 1)
+			if (this_s.size() > 1)
 			{
 				RTLIL::Wire *reduce_or_wire = new RTLIL::Wire;
 				reduce_or_wire->name = NEW_ID;
@@ -131,7 +131,7 @@ struct OptReduceWorker
 				reduce_or_cell->type = "$reduce_or";
 				reduce_or_cell->connections["\\A"] = this_s;
 				reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
-				reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.__width);
+				reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size());
 				reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 				module->cells[reduce_or_cell->name] = reduce_or_cell;
 
@@ -144,14 +144,14 @@ struct OptReduceWorker
 			handled_sig.insert(this_b);
 		}
 
-		if (new_sig_s.__width != sig_s.__width) {
+		if (new_sig_s.size() != sig_s.size()) {
 			log("    New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
 			did_something = true;
 			OPT_DID_SOMETHING = true;
 			total_count++;
 		}
 
-		if (new_sig_s.__width == 0)
+		if (new_sig_s.size() == 0)
 		{
 			module->connections.push_back(RTLIL::SigSig(cell->connections["\\Y"], cell->connections["\\A"]));
 			assign_map.add(cell->connections["\\Y"], cell->connections["\\A"]);
@@ -162,8 +162,8 @@ struct OptReduceWorker
 		{
 			cell->connections["\\B"] = new_sig_b;
 			cell->connections["\\S"] = new_sig_s;
-			if (new_sig_s.__width > 1) {
-				cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.__width);
+			if (new_sig_s.size() > 1) {
+				cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size());
 			} else {
 				cell->type = "$mux";
 				cell->parameters.erase("\\S_WIDTH");
@@ -224,7 +224,7 @@ struct OptReduceWorker
 				cell->connections["\\A"].append(in_tuple.at(0));
 
 			cell->connections["\\B"] = RTLIL::SigSpec();
-			for (int i = 1; i <= cell->connections["\\S"].__width; i++)
+			for (int i = 1; i <= cell->connections["\\S"].size(); i++)
 				for (auto &in_tuple : consolidated_in_tuples)
 					cell->connections["\\B"].append(in_tuple.at(i));
 
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 879f7ddc..4215a7b5 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -100,7 +100,7 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		}
 	}
 
-	if (sig_c.is_fully_const() && (!sig_r.__width || !has_init)) {
+	if (sig_c.is_fully_const() && (!sig_r.size() || !has_init)) {
 		if (val_rv.bits.size() == 0)
 			val_rv = val_init;
 		RTLIL::SigSig conn(sig_q, val_rv);
@@ -108,26 +108,26 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		goto delete_dff;
 	}
 
-	if (sig_d.is_fully_undef() && sig_r.__width && !has_init) {
+	if (sig_d.is_fully_undef() && sig_r.size() && !has_init) {
 		RTLIL::SigSig conn(sig_q, val_rv);
 		mod->connections.push_back(conn);
 		goto delete_dff;
 	}
 
-	if (sig_d.is_fully_undef() && !sig_r.__width && has_init) {
+	if (sig_d.is_fully_undef() && !sig_r.size() && has_init) {
 		RTLIL::SigSig conn(sig_q, val_init);
 		mod->connections.push_back(conn);
 		goto delete_dff;
 	}
 
-	if (sig_d.is_fully_const() && !sig_r.__width && !has_init) {
+	if (sig_d.is_fully_const() && !sig_r.size() && !has_init) {
 		RTLIL::SigSig conn(sig_q, sig_d);
 		mod->connections.push_back(conn);
 		goto delete_dff;
 	}
 
-	if (sig_d == sig_q && !(sig_r.__width && has_init)) {
-		if (sig_r.__width) {
+	if (sig_d == sig_q && !(sig_r.size() && has_init)) {
+		if (sig_r.size()) {
 			RTLIL::SigSig conn(sig_q, val_rv);
 			mod->connections.push_back(conn);
 		}
@@ -182,7 +182,7 @@ struct OptRmdffPass : public Pass {
 			std::vector<std::string> dff_list;
 			for (auto &it : mod_it.second->cells) {
 				if (it.second->type == "$mux" || it.second->type == "$pmux") {
-					if (it.second->connections.at("\\A").__width == it.second->connections.at("\\B").__width)
+					if (it.second->connections.at("\\A").size() == it.second->connections.at("\\B").size())
 						mux_drivers.insert(assign_map(it.second->connections.at("\\Y")), it.second);
 					continue;
 				}
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 07e512cb..819a0e46 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -97,7 +97,7 @@ struct OptShareWorker
 			RTLIL::SigSpec sig = it.second;
 			assign_map.apply(sig);
 			hash_string += "C " + it.first + "=";
-			for (auto &chunk : sig.__chunks) {
+			for (auto &chunk : sig.chunks()) {
 				if (chunk.wire)
 					hash_string += "{" + chunk.wire->name + " " +
 							int_to_hash_string(chunk.offset) + " " +