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authorClifford Wolf <clifford@clifford.at>2014-12-26 21:35:22 +0100
committerClifford Wolf <clifford@clifford.at>2014-12-26 21:35:22 +0100
commit9e6fb0b02ccf209528ead026de8eef0a8a0d7740 (patch)
treef3e7c1c9babc232a806b92a625bc447b1b75c7c4 /passes/opt
parente52d1f9b9a7f71634d4e8e8228060f792fa20dec (diff)
Replaced std::unordered_map as implementation for Yosys::dict
Diffstat (limited to 'passes/opt')
-rw-r--r--passes/opt/opt_const.cc2
-rw-r--r--passes/opt/opt_share.cc2
2 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 7f800bde..9c1a1878 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -199,7 +199,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
- dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
+ dict<RTLIL::Cell*, std::set<RTLIL::SigBit>, hash_ptr_ops> cell_to_inbit;
dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
for (auto cell : module->cells())
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index c581b749..9bc30887 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -41,7 +41,7 @@ struct OptShareWorker
CellTypes ct;
int total_count;
#ifdef USE_CELL_HASH_CACHE
- dict<const RTLIL::Cell*, std::string> cell_hash_cache;
+ dict<const RTLIL::Cell*, std::string, hash_ptr_ops> cell_hash_cache;
#endif
#ifdef USE_CELL_HASH_CACHE