Renamed RTLIL::{Module,Cell}::connections to connections_

6 files changed, 195 insertions, 195 deletions

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 00fa6031..30ab8814 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -40,7 +40,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
 	SigSet<RTLIL::Cell*> wire2driver;
 	for (auto &it : module->cells) {
 		RTLIL::Cell *cell = it.second;
-		for (auto &it2 : cell->connections) {
+		for (auto &it2 : cell->connections_) {
 			if (!ct.cell_input(cell->type, it2.first)) {
 				RTLIL::SigSpec sig = it2.second;
 				assign_map.apply(sig);
@@ -70,7 +70,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
 		for (auto cell : queue)
 			unused.erase(cell);
 		for (auto cell : queue) {
-			for (auto &it : cell->connections) {
+			for (auto &it : cell->connections_) {
 				if (!ct.cell_output(cell->type, it.first)) {
 					std::set<RTLIL::Cell*> cell_list;
 					RTLIL::SigSpec sig = it.second;
@@ -158,10 +158,10 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 		for (auto &it : module->cells) {
 			RTLIL::Cell *cell = it.second;
 			if (ct_reg.cell_known(cell->type))
-				for (auto &it2 : cell->connections)
+				for (auto &it2 : cell->connections_)
 					if (ct_reg.cell_output(cell->type, it2.first))
 						register_signals.add(it2.second);
-			for (auto &it2 : cell->connections)
+			for (auto &it2 : cell->connections_)
 				connected_signals.add(it2.second);
 		}
 	
@@ -171,7 +171,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 	for (auto &it : module->cells) {
 		RTLIL::Cell *cell = it.second;
 		if (ct_all.cell_known(cell->type))
-			for (auto &it2 : cell->connections)
+			for (auto &it2 : cell->connections_)
 				if (ct_all.cell_output(cell->type, it2.first))
 					direct_sigs.insert(assign_map(it2.second));
 	}
@@ -189,13 +189,13 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 		}
 	}
 
-	module->connections.clear();
+	module->connections_.clear();
 
 	SigPool used_signals;
 	SigPool used_signals_nodrivers;
 	for (auto &it : module->cells) {
 		RTLIL::Cell *cell = it.second;
-		for (auto &it2 : cell->connections) {
+		for (auto &it2 : cell->connections_) {
 			assign_map.apply(it2.second);
 			used_signals.add(it2.second);
 			if (!ct.cell_output(cell->type, it2.first))
@@ -237,7 +237,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 				if (new_conn.first.size() > 0) {
 					used_signals.add(new_conn.first);
 					used_signals.add(new_conn.second);
-					module->connections.push_back(new_conn);
+					module->connections_.push_back(new_conn);
 				}
 			}
 		} else {
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index e1b6c598..2a5ec8be 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -38,7 +38,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
 	SigPool all_signals;
 
 	for (auto &it : module->cells)
-	for (auto &conn : it.second->connections) {
+	for (auto &conn : it.second->connections_) {
 		if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
 			driven_signals.add(sigmap(conn.second));
 		if (!ct.cell_known(it.second->type) || ct.cell_input(it.second->type, conn.first))
@@ -66,21 +66,21 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
 			continue;
 
 		log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c));
-		module->connections.push_back(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width)));
+		module->connections_.push_back(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width)));
 		OPT_DID_SOMETHING = true;
 	}
 }
 
 static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
 {
-	RTLIL::SigSpec Y = cell->connections[out_port];
+	RTLIL::SigSpec Y = cell->connections_[out_port];
 	out_val.extend_u0(Y.size(), false);
 
 	log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
 			cell->type.c_str(), cell->name.c_str(), info.c_str(),
 			module->name.c_str(), log_signal(Y), log_signal(out_val));
 	// ILANG_BACKEND::dump_cell(stderr, "--> ", cell);
-	module->connections.push_back(RTLIL::SigSig(Y, out_val));
+	module->connections_.push_back(RTLIL::SigSig(Y, out_val));
 	module->remove(cell);
 	OPT_DID_SOMETHING = true;
 	did_something = true;
@@ -88,14 +88,14 @@ static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string i
 
 static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap)
 {
-	std::string b_name = cell->connections.count("\\B") ? "\\B" : "\\A";
+	std::string b_name = cell->connections_.count("\\B") ? "\\B" : "\\A";
 
 	bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool();
 	bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool();
 
-	RTLIL::SigSpec sig_a = sigmap(cell->connections.at("\\A"));
-	RTLIL::SigSpec sig_b = sigmap(cell->connections.at(b_name));
-	RTLIL::SigSpec sig_y = sigmap(cell->connections.at("\\Y"));
+	RTLIL::SigSpec sig_a = sigmap(cell->connections_.at("\\A"));
+	RTLIL::SigSpec sig_b = sigmap(cell->connections_.at(b_name));
+	RTLIL::SigSpec sig_y = sigmap(cell->connections_.at("\\Y"));
 
 	if (extend_u0) {
 		sig_a.extend_u0(sig_y.size(), a_signed);
@@ -160,21 +160,21 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
 
 		RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
 
-		c->connections["\\A"] = new_a;
+		c->connections_["\\A"] = new_a;
 		c->parameters["\\A_WIDTH"] = new_a.size();
 		c->parameters["\\A_SIGNED"] = false;
 
 		if (b_name == "\\B") {
-			c->connections["\\B"] = new_b;
+			c->connections_["\\B"] = new_b;
 			c->parameters["\\B_WIDTH"] = new_b.size();
 			c->parameters["\\B_SIGNED"] = false;
 		}
 
-		c->connections["\\Y"] = new_y;
+		c->connections_["\\Y"] = new_y;
 		c->parameters["\\Y_WIDTH"] = new_y->width;
 		c->check();
 
-		module->connections.push_back(new_conn);
+		module->connections_.push_back(new_conn);
 
 		log("  New cell `%s': A=%s", log_id(c), log_signal(new_a));
 		if (b_name == "\\B")
@@ -203,8 +203,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 	for (auto &cell_it : module->cells)
 		if (design->selected(module, cell_it.second)) {
 			if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") &&
-					cell_it.second->connections["\\A"].size() == 1 && cell_it.second->connections["\\Y"].size() == 1)
-				invert_map[assign_map(cell_it.second->connections["\\Y"])] = assign_map(cell_it.second->connections["\\A"]);
+					cell_it.second->connections_["\\A"].size() == 1 && cell_it.second->connections_["\\Y"].size() == 1)
+				invert_map[assign_map(cell_it.second->connections_["\\Y"])] = assign_map(cell_it.second->connections_["\\A"]);
 			cells.push_back(cell_it.second);
 		}
 
@@ -222,7 +222,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$reduce_and")
 			{
-				RTLIL::SigSpec sig_a = assign_map(cell->connections.at("\\A"));
+				RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A"));
 
 				RTLIL::State new_a = RTLIL::State::S1;
 				for (auto &bit : sig_a.to_sigbit_vector())
@@ -240,7 +240,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover("opt.opt_const.fine.$reduce_and");
 					log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
-					cell->connections.at("\\A") = sig_a = new_a;
+					cell->connections_.at("\\A") = sig_a = new_a;
 					cell->parameters.at("\\A_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -249,7 +249,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$logic_not" || cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$reduce_or" || cell->type == "$reduce_bool")
 			{
-				RTLIL::SigSpec sig_a = assign_map(cell->connections.at("\\A"));
+				RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A"));
 
 				RTLIL::State new_a = RTLIL::State::S0;
 				for (auto &bit : sig_a.to_sigbit_vector())
@@ -267,7 +267,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type);
 					log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
-					cell->connections.at("\\A") = sig_a = new_a;
+					cell->connections_.at("\\A") = sig_a = new_a;
 					cell->parameters.at("\\A_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -276,7 +276,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$logic_and" || cell->type == "$logic_or")
 			{
-				RTLIL::SigSpec sig_b = assign_map(cell->connections.at("\\B"));
+				RTLIL::SigSpec sig_b = assign_map(cell->connections_.at("\\B"));
 
 				RTLIL::State new_b = RTLIL::State::S0;
 				for (auto &bit : sig_b.to_sigbit_vector())
@@ -294,7 +294,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type);
 					log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
-					cell->connections.at("\\B") = sig_b = new_b;
+					cell->connections_.at("\\B") = sig_b = new_b;
 					cell->parameters.at("\\B_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -302,13 +302,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			}
 		}
 
-		if (cell->type == "$logic_or" && (assign_map(cell->connections.at("\\A")) == RTLIL::State::S1 || assign_map(cell->connections.at("\\B")) == RTLIL::State::S1)) {
+		if (cell->type == "$logic_or" && (assign_map(cell->connections_.at("\\A")) == RTLIL::State::S1 || assign_map(cell->connections_.at("\\B")) == RTLIL::State::S1)) {
 			cover("opt.opt_const.one_high");
 			replace_cell(module, cell, "one high", "\\Y", RTLIL::State::S1);
 			goto next_cell;
 		}
 
-		if (cell->type == "$logic_and" && (assign_map(cell->connections.at("\\A")) == RTLIL::State::S0 || assign_map(cell->connections.at("\\B")) == RTLIL::State::S0)) {
+		if (cell->type == "$logic_and" && (assign_map(cell->connections_.at("\\A")) == RTLIL::State::S0 || assign_map(cell->connections_.at("\\B")) == RTLIL::State::S0)) {
 			cover("opt.opt_const.one_low");
 			replace_cell(module, cell, "one low", "\\Y", RTLIL::State::S0);
 			goto next_cell;
@@ -320,8 +320,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" ||
 				cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow")
 		{
-			RTLIL::SigSpec sig_a = assign_map(cell->connections.at("\\A"));
-			RTLIL::SigSpec sig_b = cell->connections.count("\\B") ? assign_map(cell->connections.at("\\B")) : RTLIL::SigSpec();
+			RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A"));
+			RTLIL::SigSpec sig_b = cell->connections_.count("\\B") ? assign_map(cell->connections_.at("\\B")) : RTLIL::SigSpec();
 
 			if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr")
 				sig_a = RTLIL::SigSpec();
@@ -342,31 +342,31 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 						cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt")
 					replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx);
 				else
-					replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections.at("\\Y").size()));
+					replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections_.at("\\Y").size()));
 				goto next_cell;
 			}
 		}
 
-		if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].size() == 1 &&
-				invert_map.count(assign_map(cell->connections["\\A"])) != 0) {
+		if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections_["\\Y"].size() == 1 &&
+				invert_map.count(assign_map(cell->connections_["\\A"])) != 0) {
 			cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type);
-			replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections["\\A"])));
+			replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections_["\\A"])));
 			goto next_cell;
 		}
 
-		if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->connections["\\S"])) != 0) {
+		if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->connections_["\\S"])) != 0) {
 			cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type);
-			RTLIL::SigSpec tmp = cell->connections["\\A"];
-			cell->connections["\\A"] = cell->connections["\\B"];
-			cell->connections["\\B"] = tmp;
-			cell->connections["\\S"] = invert_map.at(assign_map(cell->connections["\\S"]));
+			RTLIL::SigSpec tmp = cell->connections_["\\A"];
+			cell->connections_["\\A"] = cell->connections_["\\B"];
+			cell->connections_["\\B"] = tmp;
+			cell->connections_["\\S"] = invert_map.at(assign_map(cell->connections_["\\S"]));
 			OPT_DID_SOMETHING = true;
 			did_something = true;
 			goto next_cell;
 		}
 
 		if (cell->type == "$_INV_") {
-			RTLIL::SigSpec input = cell->connections["\\A"];
+			RTLIL::SigSpec input = cell->connections_["\\A"];
 			assign_map.apply(input);
 			if (input.match("1")) ACTION_DO_Y(0);
 			if (input.match("0")) ACTION_DO_Y(1);
@@ -375,8 +375,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$_AND_") {
 			RTLIL::SigSpec input;
-			input.append(cell->connections["\\B"]);
-			input.append(cell->connections["\\A"]);
+			input.append(cell->connections_["\\B"]);
+			input.append(cell->connections_["\\A"]);
 			assign_map.apply(input);
 			if (input.match(" 0")) ACTION_DO_Y(0);
 			if (input.match("0 ")) ACTION_DO_Y(0);
@@ -394,8 +394,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$_OR_") {
 			RTLIL::SigSpec input;
-			input.append(cell->connections["\\B"]);
-			input.append(cell->connections["\\A"]);
+			input.append(cell->connections_["\\B"]);
+			input.append(cell->connections_["\\A"]);
 			assign_map.apply(input);
 			if (input.match(" 1")) ACTION_DO_Y(1);
 			if (input.match("1 ")) ACTION_DO_Y(1);
@@ -413,8 +413,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$_XOR_") {
 			RTLIL::SigSpec input;
-			input.append(cell->connections["\\B"]);
-			input.append(cell->connections["\\A"]);
+			input.append(cell->connections_["\\B"]);
+			input.append(cell->connections_["\\A"]);
 			assign_map.apply(input);
 			if (input.match("00")) ACTION_DO_Y(0);
 			if (input.match("01")) ACTION_DO_Y(1);
@@ -428,9 +428,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$_MUX_") {
 			RTLIL::SigSpec input;
-			input.append(cell->connections["\\S"]);
-			input.append(cell->connections["\\B"]);
-			input.append(cell->connections["\\A"]);
+			input.append(cell->connections_["\\S"]);
+			input.append(cell->connections_["\\B"]);
+			input.append(cell->connections_["\\A"]);
 			assign_map.apply(input);
 			if (input.extract(2, 1) == input.extract(1, 1))
 				ACTION_DO("\\Y", input.extract(2, 1));
@@ -440,9 +440,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			if (input.match("10 ")) {
 				cover("opt.opt_const.mux_to_inv");
 				cell->type = "$_INV_";
-				cell->connections["\\A"] = input.extract(0, 1);
-				cell->connections.erase("\\B");
-				cell->connections.erase("\\S");
+				cell->connections_["\\A"] = input.extract(0, 1);
+				cell->connections_.erase("\\B");
+				cell->connections_.erase("\\S");
 				goto next_cell;
 			}
 			if (input.match("11 ")) ACTION_DO_Y(1);
@@ -459,8 +459,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex")
 		{
-			RTLIL::SigSpec a = cell->connections["\\A"];
-			RTLIL::SigSpec b = cell->connections["\\B"];
+			RTLIL::SigSpec a = cell->connections_["\\A"];
+			RTLIL::SigSpec b = cell->connections_["\\B"];
 
 			if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
 				int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
@@ -495,8 +495,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (new_a.size() < a.size() || new_b.size() < b.size()) {
 				cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type);
-				cell->connections["\\A"] = new_a;
-				cell->connections["\\B"] = new_b;
+				cell->connections_["\\A"] = new_a;
+				cell->connections_["\\B"] = new_b;
 				cell->parameters["\\A_WIDTH"] = new_a.size();
 				cell->parameters["\\B_WIDTH"] = new_b.size();
 			}
@@ -505,24 +505,24 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 &&
 				cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1)
 		{
-			RTLIL::SigSpec a = assign_map(cell->connections["\\A"]);
-			RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
+			RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]);
+			RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
 
 			if (a.is_fully_const()) {
 				cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type);
-				std::swap(cell->connections["\\A"], cell->connections["\\B"]);
+				std::swap(cell->connections_["\\A"], cell->connections_["\\B"]);
 			}
 
 			if (b.is_fully_const()) {
 				if (b.as_bool() == (cell->type == "$eq")) {
 					RTLIL::SigSpec input = b;
-					ACTION_DO("\\Y", cell->connections["\\A"]);
+					ACTION_DO("\\Y", cell->connections_["\\A"]);
 				} else {
 					cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type);
 					cell->type = "$not";
 					cell->parameters.erase("\\B_WIDTH");
 					cell->parameters.erase("\\B_SIGNED");
-					cell->connections.erase("\\B");
+					cell->connections_.erase("\\B");
 				}
 				goto next_cell;
 			}
@@ -536,8 +536,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$or" || cell->type == "$xor")
 			{
-				RTLIL::SigSpec a = assign_map(cell->connections["\\A"]);
-				RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
+				RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]);
+				RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
 
 				if (cell->type != "$sub" && a.is_fully_const() && a.as_bool() == false)
 					identity_wrt_b = true;
@@ -548,7 +548,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr")
 			{
-				RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
+				RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
 
 				if (b.is_fully_const() && b.as_bool() == false)
 					identity_wrt_a = true, identity_bu0 = true;
@@ -556,8 +556,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$mul")
 			{
-				RTLIL::SigSpec a = assign_map(cell->connections["\\A"]);
-				RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
+				RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]);
+				RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
 
 				if (a.is_fully_const() && a.size() <= 32 && a.as_int() == 1)
 					identity_wrt_b = true;
@@ -568,7 +568,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$div")
 			{
-				RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
+				RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
 
 				if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1)
 					identity_wrt_a = true;
@@ -585,13 +585,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
 
 				if (!identity_wrt_a) {
-					cell->connections.at("\\A") = cell->connections.at("\\B");
+					cell->connections_.at("\\A") = cell->connections_.at("\\B");
 					cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH");
 					cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED");
 				}
 
 				cell->type = identity_bu0 ? "$bu0" : "$pos";
-				cell->connections.erase("\\B");
+				cell->connections_.erase("\\B");
 				cell->parameters.erase("\\B_WIDTH");
 				cell->parameters.erase("\\B_SIGNED");
 				cell->check();
@@ -603,18 +603,18 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		}
 
 		if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
-				cell->connections["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) {
+				cell->connections_["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections_["\\B"] == RTLIL::SigSpec(1, 1)) {
 			cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type);
-			replace_cell(module, cell, "mux_bool", "\\Y", cell->connections["\\S"]);
+			replace_cell(module, cell, "mux_bool", "\\Y", cell->connections_["\\S"]);
 			goto next_cell;
 		}
 
 		if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
-				cell->connections["\\A"] == RTLIL::SigSpec(1, 1) && cell->connections["\\B"] == RTLIL::SigSpec(0, 1)) {
+				cell->connections_["\\A"] == RTLIL::SigSpec(1, 1) && cell->connections_["\\B"] == RTLIL::SigSpec(0, 1)) {
 			cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type);
-			cell->connections["\\A"] = cell->connections["\\S"];
-			cell->connections.erase("\\B");
-			cell->connections.erase("\\S");
+			cell->connections_["\\A"] = cell->connections_["\\S"];
+			cell->connections_.erase("\\B");
+			cell->connections_.erase("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -628,10 +628,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			goto next_cell;
 		}
 
-		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections["\\A"] == RTLIL::SigSpec(0, 1)) {
+		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections_["\\A"] == RTLIL::SigSpec(0, 1)) {
 			cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type);
-			cell->connections["\\A"] = cell->connections["\\S"];
-			cell->connections.erase("\\S");
+			cell->connections_["\\A"] = cell->connections_["\\S"];
+			cell->connections_.erase("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -647,10 +647,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			goto next_cell;
 		}
 
-		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) {
+		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections_["\\B"] == RTLIL::SigSpec(1, 1)) {
 			cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type);
-			cell->connections["\\B"] = cell->connections["\\S"];
-			cell->connections.erase("\\S");
+			cell->connections_["\\B"] = cell->connections_["\\S"];
+			cell->connections_.erase("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -668,22 +668,22 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) {
 			RTLIL::SigSpec new_a, new_b, new_s;
-			int width = cell->connections.at("\\A").size();
-			if ((cell->connections.at("\\A").is_fully_undef() && cell->connections.at("\\B").is_fully_undef()) ||
-					cell->connections.at("\\S").is_fully_undef()) {
+			int width = cell->connections_.at("\\A").size();
+			if ((cell->connections_.at("\\A").is_fully_undef() && cell->connections_.at("\\B").is_fully_undef()) ||
+					cell->connections_.at("\\S").is_fully_undef()) {
 				cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type);
-				replace_cell(module, cell, "mux_undef", "\\Y", cell->connections.at("\\A"));
+				replace_cell(module, cell, "mux_undef", "\\Y", cell->connections_.at("\\A"));
 				goto next_cell;
 			}
-			for (int i = 0; i < cell->connections.at("\\S").size(); i++) {
-				RTLIL::SigSpec old_b = cell->connections.at("\\B").extract(i*width, width);
-				RTLIL::SigSpec old_s = cell->connections.at("\\S").extract(i, 1);
+			for (int i = 0; i < cell->connections_.at("\\S").size(); i++) {
+				RTLIL::SigSpec old_b = cell->connections_.at("\\B").extract(i*width, width);
+				RTLIL::SigSpec old_s = cell->connections_.at("\\S").extract(i, 1);
 				if (old_b.is_fully_undef() || old_s.is_fully_undef())
 					continue;
 				new_b.append(old_b);
 				new_s.append(old_s);
 			}
-			new_a = cell->connections.at("\\A");
+			new_a = cell->connections_.at("\\A");
 			if (new_a.is_fully_undef() && new_s.size() > 0) {
 				new_a = new_b.extract((new_s.size()-1)*width, width);
 				new_b = new_b.extract(0, (new_s.size()-1)*width);
@@ -699,11 +699,11 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				replace_cell(module, cell, "mux_sel01", "\\Y", new_s);
 				goto next_cell;
 			}
-			if (cell->connections.at("\\S").size() != new_s.size()) {
+			if (cell->connections_.at("\\S").size() != new_s.size()) {
 				cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type);
-				cell->connections.at("\\A") = new_a;
-				cell->connections.at("\\B") = new_b;
-				cell->connections.at("\\S") = new_s;
+				cell->connections_.at("\\A") = new_a;
+				cell->connections_.at("\\B") = new_b;
+				cell->connections_.at("\\S") = new_s;
 				if (new_s.size() > 1) {
 					cell->type = "$pmux";
 					cell->parameters["\\S_WIDTH"] = new_s.size();
@@ -718,7 +718,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 #define FOLD_1ARG_CELL(_t) \
 		if (cell->type == "$" #_t) { \
-			RTLIL::SigSpec a = cell->connections["\\A"]; \
+			RTLIL::SigSpec a = cell->connections_["\\A"]; \
 			assign_map.apply(a); \
 			if (a.is_fully_const()) { \
 				RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
@@ -732,8 +732,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		}
 #define FOLD_2ARG_CELL(_t) \
 		if (cell->type == "$" #_t) { \
-			RTLIL::SigSpec a = cell->connections["\\A"]; \
-			RTLIL::SigSpec b = cell->connections["\\B"]; \
+			RTLIL::SigSpec a = cell->connections_["\\A"]; \
+			RTLIL::SigSpec b = cell->connections_["\\B"]; \
 			assign_map.apply(a), assign_map.apply(b); \
 			if (a.is_fully_const() && b.is_fully_const()) { \
 				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \
@@ -787,13 +787,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		// be very conservative with optimizing $mux cells as we do not want to break mux trees
 		if (cell->type == "$mux") {
-			RTLIL::SigSpec input = assign_map(cell->connections["\\S"]);
-			RTLIL::SigSpec inA = assign_map(cell->connections["\\A"]);
-			RTLIL::SigSpec inB = assign_map(cell->connections["\\B"]);
+			RTLIL::SigSpec input = assign_map(cell->connections_["\\S"]);
+			RTLIL::SigSpec inA = assign_map(cell->connections_["\\A"]);
+			RTLIL::SigSpec inB = assign_map(cell->connections_["\\B"]);
 			if (input.is_fully_const())
-				ACTION_DO("\\Y", input.as_bool() ? cell->connections["\\B"] : cell->connections["\\A"]);
+				ACTION_DO("\\Y", input.as_bool() ? cell->connections_["\\B"] : cell->connections_["\\A"]);
 			else if (inA == inB)
-				ACTION_DO("\\Y", cell->connections["\\A"]);
+				ACTION_DO("\\Y", cell->connections_["\\A"]);
 		}
 
 		if (!keepdc && cell->type == "$mul")
@@ -802,9 +802,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			bool b_signed = cell->parameters["\\B_SIGNED"].as_bool();
 			bool swapped_ab = false;
 
-			RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]);
-			RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]);
-			RTLIL::SigSpec sig_y = assign_map(cell->connections["\\Y"]);
+			RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]);
+			RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]);
+			RTLIL::SigSpec sig_y = assign_map(cell->connections_["\\Y"]);
 
 			if (sig_b.is_fully_const() && sig_b.size() <= 32)
 				std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true;
@@ -820,7 +820,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n",
 							cell->name.c_str(), module->name.c_str());
 
-					module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+					module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
 					module->remove(cell);
 
 					OPT_DID_SOMETHING = true;
@@ -840,7 +840,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 								a_val, cell->name.c_str(), module->name.c_str(), i);
 
 						if (!swapped_ab) {
-							cell->connections["\\A"] = cell->connections["\\B"];
+							cell->connections_["\\A"] = cell->connections_["\\B"];
 							cell->parameters["\\A_WIDTH"] = cell->parameters["\\B_WIDTH"];
 							cell->parameters["\\A_SIGNED"] = cell->parameters["\\B_SIGNED"];
 						}
@@ -853,7 +853,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 						cell->type = "$shl";
 						cell->parameters["\\B_WIDTH"] = SIZE(new_b);
 						cell->parameters["\\B_SIGNED"] = false;
-						cell->connections["\\B"] = new_b;
+						cell->connections_["\\B"] = new_b;
 						cell->check();
 
 						OPT_DID_SOMETHING = true;
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 750a9d41..33e66e07 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -88,10 +88,10 @@ struct OptMuxtreeWorker
 			RTLIL::Cell *cell = cell_it.second;
 			if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
 			{
-				RTLIL::SigSpec sig_a = cell->connections["\\A"];
-				RTLIL::SigSpec sig_b = cell->connections["\\B"];
-				RTLIL::SigSpec sig_s = cell->connections["\\S"];
-				RTLIL::SigSpec sig_y = cell->connections["\\Y"];
+				RTLIL::SigSpec sig_a = cell->connections_["\\A"];
+				RTLIL::SigSpec sig_b = cell->connections_["\\B"];
+				RTLIL::SigSpec sig_s = cell->connections_["\\S"];
+				RTLIL::SigSpec sig_y = cell->connections_["\\Y"];
 
 				muxinfo_t muxinfo;
 				muxinfo.cell = cell;
@@ -130,7 +130,7 @@ struct OptMuxtreeWorker
 			}
 			else
 			{
-				for (auto &it : cell->connections) {
+				for (auto &it : cell->connections_) {
 					for (int idx : sig2bits(it.second))
 						bit2info[idx].seen_non_mux = true;
 				}
@@ -194,10 +194,10 @@ struct OptMuxtreeWorker
 				continue;
 			}
 
-			RTLIL::SigSpec sig_a = mi.cell->connections["\\A"];
-			RTLIL::SigSpec sig_b = mi.cell->connections["\\B"];
-			RTLIL::SigSpec sig_s = mi.cell->connections["\\S"];
-			RTLIL::SigSpec sig_y = mi.cell->connections["\\Y"];
+			RTLIL::SigSpec sig_a = mi.cell->connections_["\\A"];
+			RTLIL::SigSpec sig_b = mi.cell->connections_["\\B"];
+			RTLIL::SigSpec sig_s = mi.cell->connections_["\\S"];
+			RTLIL::SigSpec sig_y = mi.cell->connections_["\\Y"];
 
 			RTLIL::SigSpec sig_ports = sig_b;
 			sig_ports.append(sig_a);
@@ -205,7 +205,7 @@ struct OptMuxtreeWorker
 			if (live_ports.size() == 1)
 			{
 				RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size());
-				module->connections.push_back(RTLIL::SigSig(sig_y, sig_in));
+				module->connections_.push_back(RTLIL::SigSig(sig_y, sig_in));
 				module->remove(mi.cell);
 			}
 			else
@@ -222,9 +222,9 @@ struct OptMuxtreeWorker
 					}
 				}
 
-				mi.cell->connections["\\A"] = new_sig_a;
-				mi.cell->connections["\\B"] = new_sig_b;
-				mi.cell->connections["\\S"] = new_sig_s;
+				mi.cell->connections_["\\A"] = new_sig_a;
+				mi.cell->connections_["\\B"] = new_sig_b;
+				mi.cell->connections_["\\S"] = new_sig_s;
 				if (new_sig_s.size() == 1) {
 					mi.cell->type = "$mux";
 					mi.cell->parameters.erase("\\S_WIDTH");
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 073af308..7a7f02f6 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -43,7 +43,7 @@ struct OptReduceWorker
 			return;
 		cells.erase(cell);
 
-		RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]);
+		RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]);
 		std::set<RTLIL::SigBit> new_sig_a_bits;
 
 		for (auto &bit : sig_a.to_sigbit_set())
@@ -73,8 +73,8 @@ struct OptReduceWorker
 			for (auto child_cell : drivers.find(bit)) {
 				if (child_cell->type == cell->type) {
 					opt_reduce(cells, drivers, child_cell);
-					if (child_cell->connections["\\Y"][0] == bit) {
-						std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->connections["\\A"]).to_sigbit_set();
+					if (child_cell->connections_["\\Y"][0] == bit) {
+						std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->connections_["\\A"]).to_sigbit_set();
 						new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
 					} else
 						new_sig_a_bits.insert(RTLIL::State::S0);
@@ -87,23 +87,23 @@ struct OptReduceWorker
 
 		RTLIL::SigSpec new_sig_a(new_sig_a_bits);
 
-		if (new_sig_a != sig_a || sig_a.size() != cell->connections["\\A"].size()) {
+		if (new_sig_a != sig_a || sig_a.size() != cell->connections_["\\A"].size()) {
 			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
 			did_something = true;
 			OPT_DID_SOMETHING = true;
 			total_count++;
 		}
 
-		cell->connections["\\A"] = new_sig_a;
+		cell->connections_["\\A"] = new_sig_a;
 		cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size());
 		return;
 	}
 
 	void opt_mux(RTLIL::Cell *cell)
 	{
-		RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]);
-		RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]);
-		RTLIL::SigSpec sig_s = assign_map(cell->connections["\\S"]);
+		RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]);
+		RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]);
+		RTLIL::SigSpec sig_s = assign_map(cell->connections_["\\S"]);
 
 		RTLIL::SigSpec new_sig_b, new_sig_s;
 		std::set<RTLIL::SigSpec> handled_sig;
@@ -125,14 +125,14 @@ struct OptReduceWorker
 			if (this_s.size() > 1)
 			{
 				RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or");
-				reduce_or_cell->connections["\\A"] = this_s;
+				reduce_or_cell->connections_["\\A"] = this_s;
 				reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 				reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size());
 				reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 
 				RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
 				this_s = RTLIL::SigSpec(reduce_or_wire);
-				reduce_or_cell->connections["\\Y"] = this_s;
+				reduce_or_cell->connections_["\\Y"] = this_s;
 			}
 
 			new_sig_b.append(this_b);
@@ -149,14 +149,14 @@ struct OptReduceWorker
 
 		if (new_sig_s.size() == 0)
 		{
-			module->connections.push_back(RTLIL::SigSig(cell->connections["\\Y"], cell->connections["\\A"]));
-			assign_map.add(cell->connections["\\Y"], cell->connections["\\A"]);
+			module->connections_.push_back(RTLIL::SigSig(cell->connections_["\\Y"], cell->connections_["\\A"]));
+			assign_map.add(cell->connections_["\\Y"], cell->connections_["\\A"]);
 			module->remove(cell);
 		}
 		else
 		{
-			cell->connections["\\B"] = new_sig_b;
-			cell->connections["\\S"] = new_sig_s;
+			cell->connections_["\\B"] = new_sig_b;
+			cell->connections_["\\S"] = new_sig_s;
 			if (new_sig_s.size() > 1) {
 				cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size());
 			} else {
@@ -168,9 +168,9 @@ struct OptReduceWorker
 
 	void opt_mux_bits(RTLIL::Cell *cell)
 	{
-		std::vector<RTLIL::SigBit> sig_a = assign_map(cell->connections["\\A"]).to_sigbit_vector();
-		std::vector<RTLIL::SigBit> sig_b = assign_map(cell->connections["\\B"]).to_sigbit_vector();
-		std::vector<RTLIL::SigBit> sig_y = assign_map(cell->connections["\\Y"]).to_sigbit_vector();
+		std::vector<RTLIL::SigBit> sig_a = assign_map(cell->connections_["\\A"]).to_sigbit_vector();
+		std::vector<RTLIL::SigBit> sig_b = assign_map(cell->connections_["\\B"]).to_sigbit_vector();
+		std::vector<RTLIL::SigBit> sig_y = assign_map(cell->connections_["\\Y"]).to_sigbit_vector();
 
 		std::vector<RTLIL::SigBit> new_sig_y;
 		RTLIL::SigSig old_sig_conn;
@@ -211,26 +211,26 @@ struct OptReduceWorker
 		if (new_sig_y.size() != sig_y.size())
 		{
 			log("    Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
-			log("      Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections["\\A"]),
-					log_signal(cell->connections["\\B"]), log_signal(cell->connections["\\Y"]));
+			log("      Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections_["\\A"]),
+					log_signal(cell->connections_["\\B"]), log_signal(cell->connections_["\\Y"]));
 
-			cell->connections["\\A"] = RTLIL::SigSpec();
+			cell->connections_["\\A"] = RTLIL::SigSpec();
 			for (auto &in_tuple : consolidated_in_tuples)
-				cell->connections["\\A"].append(in_tuple.at(0));
+				cell->connections_["\\A"].append(in_tuple.at(0));
 
-			cell->connections["\\B"] = RTLIL::SigSpec();
-			for (int i = 1; i <= cell->connections["\\S"].size(); i++)
+			cell->connections_["\\B"] = RTLIL::SigSpec();
+			for (int i = 1; i <= cell->connections_["\\S"].size(); i++)
 				for (auto &in_tuple : consolidated_in_tuples)
-					cell->connections["\\B"].append(in_tuple.at(i));
+					cell->connections_["\\B"].append(in_tuple.at(i));
 
 			cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size());
-			cell->connections["\\Y"] = new_sig_y;
+			cell->connections_["\\Y"] = new_sig_y;
 
-			log("      New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections["\\A"]),
-					log_signal(cell->connections["\\B"]), log_signal(cell->connections["\\Y"]));
+			log("      New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections_["\\A"]),
+					log_signal(cell->connections_["\\B"]), log_signal(cell->connections_["\\Y"]));
 			log("      New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
 
-			module->connections.push_back(old_sig_conn);
+			module->connections_.push_back(old_sig_conn);
 			module->check();
 
 			did_something = true;
@@ -251,14 +251,14 @@ struct OptReduceWorker
 		for (auto &cell_it : module->cells) {
 			RTLIL::Cell *cell = cell_it.second;
 			if (cell->type == "$mem")
-				mem_wren_sigs.add(assign_map(cell->connections["\\WR_EN"]));
+				mem_wren_sigs.add(assign_map(cell->connections_["\\WR_EN"]));
 			if (cell->type == "$memwr")
-				mem_wren_sigs.add(assign_map(cell->connections["\\EN"]));
+				mem_wren_sigs.add(assign_map(cell->connections_["\\EN"]));
 		}
 		for (auto &cell_it : module->cells) {
 			RTLIL::Cell *cell = cell_it.second;
-			if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->connections["\\Q"])))
-				mem_wren_sigs.add(assign_map(cell->connections["\\D"]));
+			if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->connections_["\\Q"])))
+				mem_wren_sigs.add(assign_map(cell->connections_["\\D"]));
 		}
 
 		bool keep_expanding_mem_wren_sigs = true;
@@ -266,12 +266,12 @@ struct OptReduceWorker
 			keep_expanding_mem_wren_sigs = false;
 			for (auto &cell_it : module->cells) {
 				RTLIL::Cell *cell = cell_it.second;
-				if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->connections["\\Y"]))) {
-					if (!mem_wren_sigs.check_all(assign_map(cell->connections["\\A"])) ||
-							!mem_wren_sigs.check_all(assign_map(cell->connections["\\B"])))
+				if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->connections_["\\Y"]))) {
+					if (!mem_wren_sigs.check_all(assign_map(cell->connections_["\\A"])) ||
+							!mem_wren_sigs.check_all(assign_map(cell->connections_["\\B"])))
 						keep_expanding_mem_wren_sigs = true;
-					mem_wren_sigs.add(assign_map(cell->connections["\\A"]));
-					mem_wren_sigs.add(assign_map(cell->connections["\\B"]));
+					mem_wren_sigs.add(assign_map(cell->connections_["\\A"]));
+					mem_wren_sigs.add(assign_map(cell->connections_["\\B"]));
 				}
 			}
 		}
@@ -293,7 +293,7 @@ struct OptReduceWorker
 					RTLIL::Cell *cell = cell_it.second;
 					if (cell->type != type || !design->selected(module, cell))
 						continue;
-					drivers.insert(assign_map(cell->connections["\\Y"]), cell);
+					drivers.insert(assign_map(cell->connections_["\\Y"]), cell);
 					cells.insert(cell);
 				}
 
@@ -315,7 +315,7 @@ struct OptReduceWorker
 			{
 				// this optimization is to aggressive for most coarse-grain applications.
 				// but we always want it for multiplexers driving write enable ports.
-				if (do_fine || mem_wren_sigs.check_any(assign_map(cell->connections.at("\\Y"))))
+				if (do_fine || mem_wren_sigs.check_any(assign_map(cell->connections_.at("\\Y"))))
 					opt_mux_bits(cell);
 
 				opt_mux(cell);
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 6a35cb61..4ece182f 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -33,34 +33,34 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 	RTLIL::Const val_cp, val_rp, val_rv;
 
 	if (dff->type == "$_DFF_N_" || dff->type == "$_DFF_P_") {
-		sig_d = dff->connections["\\D"];
-		sig_q = dff->connections["\\Q"];
-		sig_c = dff->connections["\\C"];
+		sig_d = dff->connections_["\\D"];
+		sig_q = dff->connections_["\\Q"];
+		sig_c = dff->connections_["\\C"];
 		val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1);
 	}
 	else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" &&
 			(dff->type[6] == 'N' || dff->type[6] == 'P') &&
 			(dff->type[7] == 'N' || dff->type[7] == 'P') &&
 			(dff->type[8] == '0' || dff->type[8] == '1')) {
-		sig_d = dff->connections["\\D"];
-		sig_q = dff->connections["\\Q"];
-		sig_c = dff->connections["\\C"];
-		sig_r = dff->connections["\\R"];
+		sig_d = dff->connections_["\\D"];
+		sig_q = dff->connections_["\\Q"];
+		sig_c = dff->connections_["\\C"];
+		sig_r = dff->connections_["\\R"];
 		val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
 		val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
 		val_rv = RTLIL::Const(dff->type[8] == '1', 1);
 	}
 	else if (dff->type == "$dff") {
-		sig_d = dff->connections["\\D"];
-		sig_q = dff->connections["\\Q"];
-		sig_c = dff->connections["\\CLK"];
+		sig_d = dff->connections_["\\D"];
+		sig_q = dff->connections_["\\Q"];
+		sig_c = dff->connections_["\\CLK"];
 		val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
 	}
 	else if (dff->type == "$adff") {
-		sig_d = dff->connections["\\D"];
-		sig_q = dff->connections["\\Q"];
-		sig_c = dff->connections["\\CLK"];
-		sig_r = dff->connections["\\ARST"];
+		sig_d = dff->connections_["\\D"];
+		sig_q = dff->connections_["\\Q"];
+		sig_c = dff->connections_["\\CLK"];
+		sig_r = dff->connections_["\\ARST"];
 		val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
 		val_rp = RTLIL::Const(dff->parameters["\\ARST_POLARITY"].as_bool(), 1);
 		val_rv = dff->parameters["\\ARST_VALUE"];
@@ -85,16 +85,16 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		std::set<RTLIL::Cell*> muxes;
 		mux_drivers.find(sig_d, muxes);
 		for (auto mux : muxes) {
-			RTLIL::SigSpec sig_a = assign_map(mux->connections.at("\\A"));
-			RTLIL::SigSpec sig_b = assign_map(mux->connections.at("\\B"));
+			RTLIL::SigSpec sig_a = assign_map(mux->connections_.at("\\A"));
+			RTLIL::SigSpec sig_b = assign_map(mux->connections_.at("\\B"));
 			if (sig_a == sig_q && sig_b.is_fully_const()) {
 				RTLIL::SigSig conn(sig_q, sig_b);
-				mod->connections.push_back(conn);
+				mod->connections_.push_back(conn);
 				goto delete_dff;
 			}
 			if (sig_b == sig_q && sig_a.is_fully_const()) {
 				RTLIL::SigSig conn(sig_q, sig_a);
-				mod->connections.push_back(conn);
+				mod->connections_.push_back(conn);
 				goto delete_dff;
 			}
 		}
@@ -104,36 +104,36 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		if (val_rv.bits.size() == 0)
 			val_rv = val_init;
 		RTLIL::SigSig conn(sig_q, val_rv);
-		mod->connections.push_back(conn);
+		mod->connections_.push_back(conn);
 		goto delete_dff;
 	}
 
 	if (sig_d.is_fully_undef() && sig_r.size() && !has_init) {
 		RTLIL::SigSig conn(sig_q, val_rv);
-		mod->connections.push_back(conn);
+		mod->connections_.push_back(conn);
 		goto delete_dff;
 	}
 
 	if (sig_d.is_fully_undef() && !sig_r.size() && has_init) {
 		RTLIL::SigSig conn(sig_q, val_init);
-		mod->connections.push_back(conn);
+		mod->connections_.push_back(conn);
 		goto delete_dff;
 	}
 
 	if (sig_d.is_fully_const() && !sig_r.size() && !has_init) {
 		RTLIL::SigSig conn(sig_q, sig_d);
-		mod->connections.push_back(conn);
+		mod->connections_.push_back(conn);
 		goto delete_dff;
 	}
 
 	if (sig_d == sig_q && !(sig_r.size() && has_init)) {
 		if (sig_r.size()) {
 			RTLIL::SigSig conn(sig_q, val_rv);
-			mod->connections.push_back(conn);
+			mod->connections_.push_back(conn);
 		}
 		if (has_init) {
 			RTLIL::SigSig conn(sig_q, val_init);
-			mod->connections.push_back(conn);
+			mod->connections_.push_back(conn);
 		}
 		goto delete_dff;
 	}
@@ -181,8 +181,8 @@ struct OptRmdffPass : public Pass {
 			std::vector<std::string> dff_list;
 			for (auto &it : mod_it.second->cells) {
 				if (it.second->type == "$mux" || it.second->type == "$pmux") {
-					if (it.second->connections.at("\\A").size() == it.second->connections.at("\\B").size())
-						mux_drivers.insert(assign_map(it.second->connections.at("\\Y")), it.second);
+					if (it.second->connections_.at("\\A").size() == it.second->connections_.at("\\B").size())
+						mux_drivers.insert(assign_map(it.second->connections_.at("\\Y")), it.second);
 					continue;
 				}
 				if (!design->selected(mod_it.second, it.second))
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index e3e9511f..b3a37209 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -66,7 +66,7 @@ struct OptShareWorker
 		for (auto &it : cell->parameters)
 			hash_string += "P " + it.first + "=" + it.second.as_string() + "\n";
 
-		const std::map<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections;
+		const std::map<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections_;
 		std::map<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
 
 		if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" ||
@@ -135,8 +135,8 @@ struct OptShareWorker
 			return true;
 		}
 
-		std::map<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections;
-		std::map<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections;
+		std::map<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections_;
+		std::map<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections_;
 
 		for (auto &it : conn1) {
 			if (ct.cell_output(cell1->type, it.first))
@@ -180,8 +180,8 @@ struct OptShareWorker
 		}
 
 		if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) {
-			std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->connections.at("\\Q")).to_sigbit_vector();
-			std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->connections.at("\\Q")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->connections_.at("\\Q")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->connections_.at("\\Q")).to_sigbit_vector();
 			for (size_t i = 0; i < q1.size(); i++)
 				if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
 					lt = q1.at(i) < q2.at(i);
@@ -261,12 +261,12 @@ struct OptShareWorker
 				if (sharemap.count(cell) > 0) {
 					did_something = true;
 					log("  Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
-					for (auto &it : cell->connections) {
+					for (auto &it : cell->connections_) {
 						if (ct.cell_output(cell->type, it.first)) {
-							RTLIL::SigSpec other_sig = sharemap[cell]->connections[it.first];
+							RTLIL::SigSpec other_sig = sharemap[cell]->connections_[it.first];
 							log("    Redirecting output %s: %s = %s\n", it.first.c_str(),
 									log_signal(it.second), log_signal(other_sig));
-							module->connections.push_back(RTLIL::SigSig(it.second, other_sig));
+							module->connections_.push_back(RTLIL::SigSig(it.second, other_sig));
 							assign_map.add(it.second, other_sig);
 						}
 					}